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參數(shù)資料
| 型號： | U634H256BD1K45 |
| 英文描述： | NVRAM (EEPROM Based) |
| 中文描述： | NVRAM中（EEPROM的基礎(chǔ)） |
| 文件頁數(shù)： | 13/14頁 |
| 文件大小： | 239K |
| 代理商： | U634H256BD1K45 |
13
December 12, 1997
U634H256
LOW AVERAGE ACTIVE POWER
The U634H256 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
+
μ
F
0.1
100
μ
F
±
20 %
V
CAP
V
SS
Power
V
CCX
HSB
10 k
(optional,
mandatory if HSB
is used
with
Figure 1: AUTOMATIC STORE OPERATION
Schematic Diagram
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the power supply voltage level
external circuitry)
32
31
30
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AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V
CAP
5.0 V
V
SWITCH
STORE inhibit
Power Up
RECALL
t
RESTORE
24
t
DISABELING AUTOMATIC STORES: STORE CYCLE INHIBIT and AUTOMATIC POWER UP RECALL
1
μ
F
0.1
V
CAP
V
SS
Power
V
CCX
HSB
10 k
(optional,
mandatory if HSB
is used
with
Figure 2: DISABELING AUTOMATIC STORES
Schematic Diagram
external circuitry)
32
31
30
2
3
4
5
6
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8
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11
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28
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1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| U634H256BSA35 | NOVRAM|32KX8|CMOS|SOP|32PIN|PLASTIC |
| U634H256BSC25 | PRECISION LOW POWER CMOS DUAL OP-AMPS |
| U634H256BSC35 | NVRAM (EEPROM Based) |
| U634H256BSC45 | NVRAM (EEPROM Based) |
| U634H256BSK25 | NVRAM (EEPROM Based) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| U634H256BSA35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NOVRAM|32KX8|CMOS|SOP|32PIN|PLASTIC |
| U634H256BSC25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U634H256BSC35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U634H256BSC45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U634H256BSK25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
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