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參數資料
| 型號： | U3900BM-AFN |
| 英文描述： | Programmable Telephone Audio Processor |
| 中文描述： | 程控電話音頻處理器 |
| 文件頁數： | 33/34頁 |
| 文件大?。?/td> | 762K |
| 代理商： | U3900BM-AFN |
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U3900BM
Rev. A2, 25-Aug-98
Target Specification
8 (34)
The filter outputs are smoothed and then limited by high-
gain comparators which have hysteresis to reduce
sensitivity to unwanted low-level signals, jitter and noise.
The outputs of the comparators are square-wave signals.
The two resulting rectangular waves are applied to the
digital circuitry where a counting algorithm measures and
averages their periods. This averaging prevents dual-tone
SCWID simulation by extraneous signals such as voice.
The averaging algorithm has been optimized to provide
excellent immunity to “talk-off” and tolerance to the
presence of interfering frequencies (third tones) and
noise.
When both digital circuitries simultaneously detect a
valid tone (2130 Hz and 2750 Hz), the signal applied at
the guard-time block goes high. Should the alert tone
signal be lost, the input signal at the guard-time block will
go low.
2.2.3
Guard Time, Overview
To prevent false detection due to talk-off effects and to
detect real CAS signals even with drops, a guard-time
system is necessary. A guard-time system improves the
detection performance and verifies that the duration of a
valid
signal
is
sufficient
before
alerting
the
microprocessor with an interrupt. It rejects detection of
insufficient duration (up guard time) and mask dropouts
(down guard time).
There are nine bits for controlling the guard-time block:
D 2 bits, EGT0 and EGT1, for controlling the early
guard time
D 2 bits, UGT0 and UGT1, for controlling the up guard
time
D 2 bits, DGT0 and DGT1, for controlling the down
guard time
D 1 bit, FFD, for controlling the width filter
D 1 bit, FDC, for controlling the drops count
D 1 bit, WP, for enabling the wetting pulse function
One bit is dedicated for enabling the SCWID part.
2.2.4
Up Guard Time, Description
The up guard time circuitry prevents false detection from
speech or music (talk-off).
The input signal (both 2130 Hz and 2750 Hz) must be
continuously high for a duration depending on the
2 programmable bits UGT0 and UGT1.
DGT0
DGT1
UGT Value
0
20 ms
1
0
25 ms
0
1
30 ms
1
35 ms
If a drop occurs at any time before the selected value, the
detection system is cleared.
Nevertheless, there is the possibility to improve such a
system using early guard time circuitry.
2.2.5
Early Guard Time, Description
The early guard time system, when enabled, helps the up
guard time to detect a CAS signal even if there are drops
in it. But there are conditions before validating such a
polluted signal.
The input signal (both 2130 Hz and 2750 Hz) must be
continuously high for duration depending on the
2 programmable bits EGT0 and EGT1.
EGT0
EGT1
EGT Value
0
Disabled
1
0
8.5 ms
0
1
10.3 ms
1
13.7 ms
After that, the input signal is filtered and a drop can occur
without clearing the system if it is not too long . The
maximum time value depends on the command filter bit
FFD.
FFD
Filter Value
(Maximum Drop Duration)
0
2 ms
1
4 ms
If there are too many drops, the system is cleared. The
count of drops admitted depends on the command count
bit FDC.
FDC
Count Value
(Maximum Drop Count)
0
4
1
3
The early guard time with filter and count drops allow a
good compromise to achieve talk-off and talk-down
immunity.
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