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參數(shù)資料
| 型號： | U2894B-AFSG3 |
| 英文描述： | Modulation PLL for GSM, DCS and PCS Systems |
| 中文描述： | 調(diào)制鎖相環(huán)用于GSM，DCS和PCS系統(tǒng) |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 802K |
| 代理商： | U2894B-AFSG3 |
U2894B
Rev. A4, 30-Sep-98
11 (16)
Application Circuit for DCS1800 (1710 – 1785 MHz)
N1
divider
R1
divider
Mode
control
16
17
13
14
15
MUX
90
°
Voltage
reference
I/Q modulator
5
6
25
20
19
12
27
28
3
2
1
Mixer
PFD
Charge
pump
10
11
24
18
4
22
23
8
9
7
21
26
14570
15 nH
2x
15 pF
200
f_LO (–10 dBm)
1310–1385 MHz
Baseband processor
50
2.7 to 3.5 V
+
f_Ref
V
rms = 55 mV
(400 MHz)
50
68 pF
VCO
2.7 to 3.5 V
2.7
to 3.5 V
6 dB
attn.
390
MQE5A1–1747
390
3.3 nF
f_TX
(1710–
1785 MHz)
to PA
4.7 pF
820
24 nH
2 pF
4.7 pF
12 nH
Attention!
Differential source impedance
seen by the I/NI, Q/NQ inputs
should not exceed 1000 Ohms
r_diff
36 k
Figure 16. Application circuit (power-up and charge-pump control is not shown)
Measurements
Modulation-Loop Settling Time
As valid for all PLL loops the settling time depends on
several factors. The following figure is an extraction from
measurements performed in an arrangement like the ap-
plication circuit. It shows that a loop settling time of a few
ms can be achieved.
CPC: 1 k
to GND
CPC ‘open’
Vertical: VCO tuning voltage 1 V/Div
Horizontal: Time 1
ms/Div
Figure 17.
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