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參數(shù)資料
| 型號(hào)： | U2894B-AFSG3 |
| 英文描述： | Modulation PLL for GSM, DCS and PCS Systems |
| 中文描述： | 調(diào)制鎖相環(huán)用于GSM，DCS和PCS系統(tǒng) |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 802K |
| 代理商： | U2894B-AFSG3 |
U2894B
Rev. A4, 30-Sep-98
7 (16)
Mode Selection
The device can be programmed to different modes via an external resistor RMODE (including short, open) from Pin MC
to VS2. The mode is distinguished from specific N-, R-divider ratios, and the polarity of the charge pump current.
Mode Selection
N-Divider
R-Divider
CPO Current Polarity 4)
Application
Mode
Resistance between
Pin MC and Pin VS2
fN < fR 1)
fN > fR 1)
1
0 (<50
W)
1:1
Sink
Source
2
2.7 k
W (±5%)
1:1
Source
Sink
3
10 k
W (±5%)
1:1
2:1
Source
Sink
4
36 k
W (±5%)
2:1
Source
Sink
PCN/PCS 2)
5
R (>1 MW)
2:1
Sink
Source
GSM 3)
1)
Frequencies referred to PFD input
2)
LO frequencies below VCO frequency
3)
LO frequencies above VCO frequency
4)
Sink current into Pin CPO. Source: current out from Pin CPO.
Equivalent Circuits at the IC’s Pins
L,Q
NI, NQ
250
30 pF
2230
2230
VS1
MDO
NMDO
GND
Baseband input
LO input
Output
14553
MDLO
V
Bias_MDLO
V
Ref_input
V
Ref_MDLO
V
Ref_output
Figure 5. I/Q modulator
14554
NRF
LO input
890
890
1 k
Output
1.6 k
1.6 k
1 k
RF
MIXLO
40 pF
6.3
MIXO
VS3
GND
V
Bias_RF
V
Ref_RF
V
Bias_LO
V
Ref_LO
Figure 6. Mixer
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