參數(shù)資料
型號: U2782B-AFSG3
英文描述: 1100 MHz Twin PLL
中文描述: 1100兆赫雙鎖相環(huán)
文件頁數(shù): 7/10頁
文件大小: 159K
代理商: U2782B-AFSG3
U2782B
TELEFUNKEN Semiconductors
Rev. A4, 17-Oct-97
7 (10)
Timing Diagram Serial Bus
t
SEC
t
CH
t
CL
t
EL
t
HEC
t
HCE
t
SDC
t
HDC
Data
Clock
Enable
Internal
Loadpulse
96 11828
Clock High Time
Clock Low Time
Clock Period
Set up Time Clock Data to Clock
Hold Time Data to Clock
Hold Time Clock to Enable
Hold Time Enable to Clock
Enable Low Time
Set up Time Enable to Clock
t
CH
t
CL
t
PER
t
SDC
t
HDC
t
HCE
t
HEC
t
EL
t
SEC
>750
>350
>1100
>100
>400
>400
>400
>200
>4000
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
3000
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
30000
300000
I
R19/
96 11679
5 I = 1
Figure 3. Charge pump characteristics
1
10
100
1000
0
200
400
600
800
1000 1200
1
Frequency/ MHz
96 11680
Guaranteed Area
Figure 4. Input sensitivity of PLL1 and PLL2
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