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參數(shù)資料
| 型號(hào)： | U2782B-AFSG3 |
| 英文描述： | 1100 MHz Twin PLL |
| 中文描述： | 1100兆赫雙鎖相環(huán) |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 159K |
| 代理商： | U2782B-AFSG3 |
U2782B
TELEFUNKEN Semiconductors
Rev. A4, 17-Oct-97
4 (10)
Serial Bus Programming
Reference
and
programmed by the 3-wire-bus (Clock, Data and Enable).
After setting enable signal to high condition, the data sta-
tus is transfered but by but on the rising edge of the clock
signal into the shift register, starting with the MSB-bit.
After the Enable signal returns to low condition the
programmed information is loaded according to the
addressbits (last three bits) into the addressed latch.
Additional leading bits are ignored and there is no check
made how many clock pulses arrived during enable high
condition. In powerdown mode the 3-wire-bus remains
active and the IC can be programmed.
programmable
counters
can
be
Data is entered with the most significant bit first. The
leading bits deliver the divider or control information.
The trailing three bits are the address field. There are six
different addresses used. The trailing address bits are
decoded upon the falling edge of the Enable signal. The
internal Loadpulse is beginning with the falling edge of
the Enable signal and ending with falling edge of the
Clock signal. Therefore a minimum holdtime clock-
enable t
HCE
is required.
Bit Allocation
MSB
Bit
1
2
LSB
Bit
20
Bit
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
8
Bit
9
Bit
10
Bit
11
Bit
12
Bit
13
Bit
14
Bit
15
Bit
16
Bit
17
Bit
18
Bit
19
data bits
D8
address bits
A2
A1
D16 D15 D14 D13 D12
D11
D10
D9
D7
D6
D5
D4
D3
D2
D1
D0
A0
PLL1
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
S5
S4
S3
S2
S1
PLL1
S0
0
0
1
PLL1
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
PL1
R0
0
1
0
PLL2
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
S5
S4
S3
S2
S1
PLL2
S0
0
1
1
PLL2
R11
TRI
1
R10
PS2
R9
PS1
R8
H2P H1P
R7
R6
LP
B
R5
LPA
R4
P4
R3
P3
R2
P2
R1
P1
PLL2
R0
P0
1
1
0
0
0
1
RF/
2
Test
5IP
TRI
2
SP
D 5I
SP
D 2
SP
D 1
1
1
0
Scaling Factors
S0 ... S5:
These bits are setting the swallow counter S
S
.
T
S
= S0*2
0
+ S1*2
1
+ ... + S4*2
4
+ S5*2
5
allowed scalling factors for S
S
: 0 ... 63, T
S
< T
M
M0 ... M10: These bits are setting the main counter S
M
.
T
M
= M0*2
0
+ M1*2
1
+ ... + M9*2
9
+ M10*2
10
allowed scalling factors for S
M
: 5 ... 2047
S
PGD
: Total scalling factor of the programmable counter:
S
PGD
= (64*S
M
) + S
S
Condition: S
S
< S
M
R0 ... R11:
These bits are setting the reference counter S
R
.
S
R
= R0*2
0
+ ... + R10*2
10
+ R11*2
11
allowed scalling factors for S
R
: 5 ... 4096
S
RFD
: Total scalling factor of the reference counter:
RF/2 = 1:
S
RFD
= 2 * S
R
RF/2 = 0:
S
RFD
= S
R
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| U2784B | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:2200 MHz / 200 MHz Twin PLL |
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