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參數(shù)資料
| 型號： | TZA3044T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | 1.25 Gbits/s Gigabit Ethernet postamplifiers |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 封裝： | PLASTIC, SO-16 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 104K |
| 代理商： | TZA3044T |
1998 Jul 07
5
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
Bonding pad locations
Fig.3 Bonding pad locations: TZA3044U.
(1) Typical value.
Pad size: 90
×
90
μ
m.
handbook, full pagewidth
AGND
4
VCCD
27
TEST
26
DGND
25
DOUT
24
DOUTQ
23
DGND
22
TEST
21
DGND
20
AGND
6
DIN
7
DINQ
8
AGND
9
TEST
10
VCCA
11
n.c.
5
TZA3044U
12
V
3
A
2
T
1
S
32
n
31
n
30
R
29
V
28
V
13
C
14
S
15
T
16
J
17
S
18
S
19
D
MGR242
1.58 mm
(1)
1.58
(1)
mm
x
y
0
0
FUNCTIONAL DESCRIPTION
The TZA3044 accepts up to 1.25 Gbits/s Gigabit Ethernet
data streams, with amplitudes from 2 mV (p-p) up to
1 V (p-p) single-ended. The input signal will be amplified
and limited to differential PECL output levels (see Fig.1).
The input buffer A1 presents an impedance of
approximately 4.5 k
to the data stream on the inputs DIN
and DINQ. The input can be used both single-ended and
differential, but differential operation is preferred for better
performance.
Because of the high gain of the postamplifier, a very small
offset voltage would shift the decision level in such a way
that the input sensitivity decreases drastically. Therefore a
DC offset compensation circuit is implemented in the
TZA3044, which keeps the input of buffer A3 at its toggle
point in the absence of any input signal.
An input signal level detection is implemented to check if
the input signal is above the user-programmed level.
The outcome of this test is available at the PECL
outputs ST and STQ. This flag can also be used to prevent
the PECL outputs DOUT and DOUTQ from reacting to
noise in the absence of a valid input signal, by connecting
the output STQ to the input JAM. This insures that data will
only be transmitted when the input signal-to-noise ratio is
sufficient for low bit error rate system operation.
PECL logic
The logic level symbol definitions for PECL are shown in
Fig.4.
Input biasing
The input pins DIN and DINQ are DC biased at
approximately 2.55 V by an internal reference generator
(see Fig.5). The TZA3044 can be DC coupled, but AC
coupling is preferred. In case of DC coupling, the driving
source must operate within the allowable input signal
range (2.0 V to V
CCA
+ 0.5 V). Also a DC offset voltage of
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| TZA3044 | SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers |
| TZA3044B | SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers |
| TZA3044BT | SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers |
| TZA3044BTT | SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TZA3044TT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers |
| TZA3044U | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.25 Gbits/s Gigabit Ethernet postamplifiers |
| TZA3047A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:30 Mbits/s up to 1.25 Gbits/s laser drivers |
| TZA3047AVH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:30 Mbits/s up to 1.25 Gbits/s laser drivers |
| TZA3047B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:30 Mbits/s up to 1.25 Gbits/s laser drivers |
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