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參數(shù)資料
| 型號： | TZA3044T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 1.25 Gbits/s Gigabit Ethernet postamplifiers |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 封裝： | PLASTIC, SO-16 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 104K |
| 代理商： | TZA3044T |
1998 Jul 07
3
Philips Semiconductors
Objective specification
1.25 Gbits/s Gigabit Ethernet postamplifiers
TZA3044T; TZA3044U
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
SUB
TEST
AGND
DIN
1
2
3
4
substrate
test pin
ground
analog input
substrate pin; must be at the same potential as AGND (pin 3)
for test purpose only; to be left open in the application
analog ground; must be at the same potential as DGND (pin 11)
differential input; DC bias level is set internally at approximately 2.55 V;
complimentary to DINQ (pin 5)
differential input; DC bias level is set internally at approximately 2.55 V;
complimentary to DIN (pin 4)
analog supply voltage; must be at the same potential as V
CCD
(pin 14)
filter capacitor for input signal level detector; capacitor should be connected
between this pin and V
CCA
(pin 6)
PECL-compatible input; controls the output buffers DOUT and DOUTQ
(pins 13 and 12). When a LOW signal is applied, the outputs will follow the input
signal. When a HIGH signal is applied, the DOUT and DOUTQ pins will latch into
LOW and HIGH states, respectively. When left unconnected, this pin is actively
pulled LOW (JAM OFF).
PECL-compatible status output of the input signal level detector; when the input
signal is below the user-programmed threshold level, this output is HIGH;
complimentary to ST (pin 10)
PECL-compatible status output of the input signal level detector; when the input
signal is below the user-programmed threshold level, this output is LOW;
complimentary to STQ (pin 9)
digital ground; must be at the same potential as AGND (pin 3)
PECL-compatible differential output; when JAM is HIGH, this pin will be forced
into a HIGH condition; complimentary to DOUT (pin 13)
PECL-compatible differential output; when JAM is HIGH, this pin will be forced
into a LOW condition; complimentary to DOUTQ (pin 12)
digital supply voltage; must be at the same potential as V
CCA
(pin 6)
analog output band gap reference voltage; typical value is 1.2 V; internal series resistor of 1 k
analog input
input signal level detector programming; nominal DC voltage is V
CCA
1.5 V;
threshold level is set by connecting an external resistor between RSET and V
CCA
or by forcing a current into RSET; default value for this resistor is 180 k
which
corresponds with approximately 4 mV (p-p) differential input signal
DINQ
5
analog input
V
CCA
CF
6
7
supply
analog input
JAM
8
PECL input
STQ
9
PECL output
ST
10
PECL output
DGND
DOUTQ
11
12
ground
PECL output
DOUT
13
PECL output
V
CCD
V
ref
RSET
14
15
16
supply
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TZA3044 | SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers |
| TZA3044B | SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers |
| TZA3044BT | SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers |
| TZA3044BTT | SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers |
| TZA3044BU | SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TZA3044TT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers |
| TZA3044U | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.25 Gbits/s Gigabit Ethernet postamplifiers |
| TZA3047A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:30 Mbits/s up to 1.25 Gbits/s laser drivers |
| TZA3047AVH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:30 Mbits/s up to 1.25 Gbits/s laser drivers |
| TZA3047B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:30 Mbits/s up to 1.25 Gbits/s laser drivers |
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