參數(shù)資料
型號(hào)： TZA3034TT
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： SDH/SONET STM1/OC3 postamplifier
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PDSO16
封裝： PLASTIC, TSSOP-16
文件頁(yè)數(shù)： 4/28頁(yè)
文件大小： 143K
代理商： TZA3034TT
1999 Nov 03
4
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
PINNING
Note
1.
Pin type abbreviations: O = Output, I = Input, S = power Supply and A = Analog function.
SYMBOL
PIN
TZA3034T
TZA3034TT
PAD
TZA3034U
TYPE
(1)
DESCRIPTION
SUB
TEST
1
2
1, 14
2, 10, 15,
21, 26
3, 4, 6, 9
7
S
substrate pin; must be at the same potential as pin AGND
for test purpose only; to be left open in the application
AGND
DIN
3
4
S
I
analog ground; must be at the same potential as pin DGND
differential input; complementary to pin DINQ; DC bias level is set
internally at approximately 2.1 V
differential input; complementary to pin DIN; DC bias level is set
internally at approximately 2.1 V
analog supply voltage; must be at the same potential as pin V
CCD
input for connection of capacitor to set time constant of level detector
input filter (optional); the capacitor should be connected between
V
CCA
and pin CF
PECL-compatible input; controls the output buffers,
pins DOUTand DOUTQ; when a LOW signal is applied, the output
buffers will follow the input signal; when a HIGH signal is applied, the
output buffers will latch into LOW and HIGH states respectively;
when not connected, pin JAM is actively pulled LOW
PECL-compatible status output of the input signal level detector;
when the input signal is below the user-programmed threshold level,
this output is HIGH; complementary to pin ST
PECL-compatible status output of the input signal level detector;
when the input signal is below the user-programmed threshold level,
this output is LOW; complementary to pin STQ
digital ground; must be at the same potential as pin AGND
DINQ
5
8
I
V
CCA
CF
6
7
11, 12
13
S
A
JAM
8
16
I
STQ
9
17
O
ST
10
18
O
DGND
11
19, 20, 22,
25
23
S
DOUTQ
12
O
PECL-compatible differential output; this pin will be forced into a
HIGH condition when pin JAM is HIGH; complementary to pin DOUT
PECL-compatible differential output; this pin will be forced into a
LOW condition when pin JAM is HIGH; complementary to
pin DOUTQ
digital supply voltage; must be at the same potential as V
CCA
band gap reference voltage; typical value is 1.2 V; internal series
resistor of 1 k
input signal level detector threshold setting; nominal DC voltage is
V
CCA
1.5 V; threshold level is set by connecting an external resistor
between V
CCA
and pin RSET or by forcing a current into pin RSET;
default value for this resistor is 180 k
which corresponds with
approximately 4 mV (p-p) differential input signal
not connected
DOUT
13
24
O
V
CCD
V
ref
14
15
27, 28
29
S
O
RSET
16
30
A
n.c.
5, 31, 32
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