參數(shù)資料
型號: TVP6000C
廠商: Texas Instruments, Inc.
英文描述: NTSC/PAL Digital Video Encoder
中文描述: NTSC / PAL數(shù)字視頻編碼器
文件頁數(shù): 41/57頁
文件大?。?/td> 268K
代理商: TVP6000C
2–29
2.11.25 BMRQ
Subaddress: 71
7
6
5
4
3
2
1
0
BMRQ[7:0]
Beginning of master request.
Where:
BMRQ[7:0] These bits define the starting pixel position on a horizontal display line where active
video will be displayed. The upper three bits, BMRQ[10:8], reside in register
BEMRQ, subaddress 73. These settings shape the RCM2 pin output.
2.11.26 EMRQ
Subaddress: 72
7
6
5
4
3
2
1
0
EMRQ[7:0]
End of master request.
Where:
EMRQ[7:0] These bits define the ending pixel position on a horizontal display line where active
video will end. The upper three bits, EMRQ[10:8], reside in register BEMRQ,
subaddress 73. These settings shape the RCM2 pin output.
2.11.27 BEMRQ
Subaddress: 73
15
14
13
12
11
10
9
8
EMRQ[10:8]
BMRQ[10:8]
Overflow register for master request.
Where:
EMRQ[10:8]
BMRQ[10:8]
Upper three bits of register EMRQ. See EMRQ register definition
Upper three bits of register BMRQ. See BMRQ register definition
2.11.28 BRCV
Subaddress: 77
7
6
5
4
3
2
1
0
BRCV[7:0]
Beginning of raster control, RCV2, out.
Where:
BRCV[7:0] These bits along with the CBLFV2 bit in the SYN_CTRL0 register defines the
beginning of the active output at pin RCV2. The upper three bits of this register are in
register BERCV, subaddress 79.
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