參數(shù)資料
型號(hào)： TSS461E
廠商： Atmel Corp.
英文描述： VAN Data Link Controller
中文描述： 凡數(shù)據(jù)鏈路控制器
文件頁(yè)數(shù)： 6/57頁(yè)
文件大?。?/td> 817K
代理商： TSS461E
6
TSS461E
4194B–AUTO–12/04
Microprocessor
Interface
The processor controls the TSS461E by reading and writing the internal registers of the
circuit. These registers appear to the processor as regular memory locations.
Interface Modes
The TSS461E must be plugged in an Intel or Motorola environment with an 8-bit
address/data bus multiplexed.
Table 1.
Access Mode Logic
In Intel environment, access operations need CS active, a read one with RD active, a
write one with WR active. If TSS461E is the single peripheral in the processor space,
CS can be wired to VCC.
In Motorola environment, the RD pin is wired to VSS and the access operations are
driven by CS (E). Contrary to Intel mode, CS (E) must never be wired to Vcc even if the
TSS461E is alone.
To switch on-the-fly from one mode to the other, CS must be inactive.
Intel Mode
The Intel mode interface consists of 13 pins. 8 pins are the multiplexed address and
data bus, and the rest are the address strobe, the read and write commands, the chip
select and the interrupt request pins.
To access the memory locations in Intel mode, the processor must first assert a valid
address on the multiplexed address and data bus and drive the address strobe pin high.
When the required set up time has passed, the processor must drive the address strobe
low, and keep the address valid for the required hold time.
The processor must then either assert the data to be written on the address and data
bus, if a write is intended, or float the data bus for a read. The next step is to drive either
the write or read command pins low, according to the function required, and at the same
time drive the chip select pin high.
The TSS461E access cycle is then terminated by driving the chip select and command
pins low.
Note:
that the chip select pin may be driven high for the entire access cycle, and may also
remain high during and after the termination of the cycle.
CS (E)
RD
WR (R/W)
Operation Mode
0
No operation
1
0
0
Write Operation in Motorola mode
1
0
1
Read operation in both modes
1
1
0
Write operation in Intel mode
1
1
1
No operation
相關(guān)PDF資料
PDF描述
TSS461E-TDRA-9 VAN Data Link Controller
TSS461E-TERA-9 VAN Data Link Controller
TSS461E-TRDZ-9 VAN Data Link Controller
TSS461F VAN Data Link Controller
TSS463-AAR VAN Data Link Controller with Serial Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSS461E_06 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:VAN Data Link Controller
TSS461E-TDRA-9 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:VAN Data Link Controller
TSS461E-TDRZ-9 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:VAN Data Link Controller
TSS461E-TDSA-9 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:VAN Data Link Controller
TSS461E-TERA-9 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:VAN Data Link Controller
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