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參數(shù)資料
| 型號： | TSS461E-TDRA-9 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | VAN Data Link Controller |
| 中文描述： | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDSO24 |
| 封裝： | SOP-24 |
| 文件頁數(shù)： | 21/57頁 |
| 文件大?。?/td> | 817K |
| 代理商： | TSS461E-TDRA-9 |
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21
TSS461E
4194B–AUTO–12/04
If there are less than four edges during one SDC period, the diagnosis mode will
change to the major error mode.
Transmission diagnosis:
The transmission compares RxD1 and RxD2 inputs (through the input comparators
and the filters) with the data transmitted on TxD output.
At a time when the transmission logic generates a dominant (recessive transition),
the inputs can give different values. Taking into account the filtering delay, the bus
line seen as dominant is assumed to be correct, the other one, recessive, is
considered faulty. The diagnosis mode is changed to reflect that.
Protocol fault:
The protocol fault is detected by counting the number of consecutive dominant
timeslots.
If eight consecutive timeslots are dominant, the diagnosis mode will change to the
major error mode.
Generation of Internal
Signals
RI Signal (Return to Idle)
This signal is used to return to nominal mode in the three specified selection modes (see
section “Diagnosis States” and section “Programming Modes”). The RI signal is dis-
abled in automatic selection mode.
The RI signal is a pulse generated when an EOF is detected. So, at the end of each
frame, the user, regarding the diagnosis status bit Sa, Sb & Sc, can select its own
choice.
SDC Signal (Synchronous
Diagnosis Clock)
This time base is used by diagnosis system in automatic selection mode (see
section “Programming Modes”) when no event is recorded on the bus.
The SDC is generated either by a special SDC divider connected to the timeslot clock,
or manually. The SDC clock period must be longer compared to the timeslot duration.
A typical SDC period should be greater than the maximum frame length appearing on
the VAN network.
TIP Signal (Transmission In
Progress)
This signal must be enabled to allow the transmission diagnosis (see section “Transition
Analyses”).
The TIP turns on synchronously at the beginning of the transmission:
For asynchronous bus access, the beginning of SOF,
For synchronous bus access, the beginning of the identifier field,
For a request of in frame reply, the RTR bit of the command field.
The TIP turns off synchronously at the end of the transmission:
after EOF
after a losing of arbitration or a code violation detection
for a requester of in frame reply, when the arbitration is lost on RTR the bit.
This signal is not generated when the transmission logic only sends an ACK.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSS461E-TERA-9 | VAN Data Link Controller |
| TSS461E-TRDZ-9 | VAN Data Link Controller |
| TSS461F | VAN Data Link Controller |
| TSS463-AAR | VAN Data Link Controller with Serial Interface |
| TSS463A-TERZ | VAN Data Link Controller with Serial Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSS461E-TDRZ-9 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:VAN Data Link Controller |
| TSS461E-TDSA-9 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:VAN Data Link Controller |
| TSS461E-TERA-9 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:VAN Data Link Controller |
| TSS461E-TRDZ-9 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:VAN Data Link Controller |
| TSS461F | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:VAN Data Link Controller |
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