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參數(shù)資料
| 型號： | TSL3301CL |
| 廠商： | AMS-TAOS USA Inc |
| 文件頁數(shù)： | 11/21頁 |
| 文件大?。?/td> | 659K |
| 描述： | IC LINEAR SENSOR ARRAY 8CHIPLED |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| 其它名稱： | TSL3301-CLDKR |
TSL3301CL
102 ?1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 JULY 2011
10
r
r
Copyright E 2011, TAOS Inc.
The LUMENOLOGY r Company
www.taosinc.com
Light-to-Digital Transfer Characteristics at V
DD
= 5 V, T
J
= 25?/SPAN>C, ?/SPAN>
p
= 660 nm, t
int
= 250 ?/SPAN>s (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A-to-D converter resolution
8
Bits
Gain register = 00000b
3.6
Full-scale reference
Gain register = 11111b
1.24
nJ/cm
2
Full-scale reference temperature sensitivity
For converter only, does not include
photodiode characteristics
?50
ppm/癈
Gain register = 00000b
0
7
30
Average dark-level offset
Gain register = 11111b
Offset register = 00000000b
20
LSB
Gain register = 00000b, see Note 1
5
10
Dark signal nonuniformity (DSNU)
Gain register = 11111b, see Note 1
14
LSB
Offset re ister =
Gain register = 00000b
Ee = 11.3 糤/cm
2
160
200
240
Average white level output
=
00000000b
Gain register = 11111b
Ee = 3.77 糤/cm
2
200
LSB
Pixel-response non-uniformity (PRNU)
Ee = 11.3 糤/cm
2
, See Notes 2 and 3
?
?0
%
Programmable offset steps
?28
Gain register = 00000b
0.5
Programmable offset step size
Gain register = 11111b
1.5
LSB
Dark-level change with temperature
0癈 < T
J
< 70?/SPAN>C
2
LSB
Differential nonlinearity
?.5
LSB
Integral nonlinearity
?
LSB
Gain register = 00000b
0.5
Dark level noise
Gain register = 11111b
1.5
LSB
NOTES: 1. DSNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is not
illuminated.
2. PRNU does not include DSNU.
3. PRNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is uniformly
illuminated at nominal white level (typical average output level = 200).
Timing Requirements over recommended operating range (unless otherwise noted) (Figure 2)
MIN
NOM
MAX
UNIT
f
max
Maximum clock frequency
10
MHz
t
w(CLKH)
Clock high pulse duration
30
ns
t
w(CLKL)
Clock low pulse duration
30
ns
t
su
Input setup time
20
ns
t
h
Input hold time
20
ns
Switching Characteristics over recommended operating range (unless otherwise noted) (Figure 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
r
Rise time, output
10
ns
t
f
Fall time, output
C
L
= 20 pF
10
ns
t
d
Delay from clock edge to data-out stable
20
ns
C
i
Input pin capacitance
10
pF
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