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參數(shù)資料
| 型號(hào)： | TSC80251G2D-24IA |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8/16-bit Microcontroller with Serial Communication Interfaces |
| 中文描述： | 16位產(chǎn)品微控制器的串行通信接口 |
| 文件頁(yè)數(shù)： | 15/63頁(yè) |
| 文件大?。?/td> | 878K |
| 代理商： | TSC80251G2D-24IA |
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Rev. A - May 7, 1999
15
TSC80251G2D
UCONFIG1
Configuration Byte 1
Notes:
1. The CSIZE is only available on EPROM/OTPROM products.
2. Two or four bytes are transparently popped according to INTR when using the RETI instruction. INTR must be set if interrupts are used
with code executing outside region FF:.
3. Use only for Step A compatibility; set this bit when WSB1:0# are used.
Figure 8. Configuration Byte 1
Table 13. Address Ranges and Usage of RD#, WR# and PSEN# Signals
Note:
1. This selection provides compatibility with the standard 80C51 hardware which has separate external memory spaces for data and code.
7
6
5
4
3
2
1
0
CSIZE
-
-
INTR
WSB
WSB1#
WSB0#
EMAP#
Bit Number
Bit Mnemonic
Description
7
CSIZE
TSC87251G2D
On-Chip Code Memory Size bit
(1)
Clear to select 16 Kbytes of on-chip code memory (TSC87251G1D product).
Set to select 32 Kbytes of on-chip code memory (TSC87251G2D product).
-
TSC80251G2D
TSC83251G2D
Reserved
Set this bit when writing to UCONFIG1.
6
-
Reserved
Set this bit when writing to UCONFIG1.
5
-
Reserved
Set this bit when writing to UCONFIG1.
Interrupt Mode bit
(2)
Clear so that the interrupts push two bytes onto the stack (the two lower bytes of the PC register).
Set so that the interrupts push four bytes onto the stack (the three bytes of the PC register and the
PSW1 register).
Wait State B bit
(3)
Clear to generate one wait state for memory region 01:.
Set for no wait states for memory region 01:.
4
INTR
3
WSB
2
WSB1#
Wait State B bits
Select the number of wait states for RD#, WR# and PSEN# signals for external memory accesses
(only region 01:).
WSB1#
WSB0#
Number of Wait States
0
0
3
0
1
2
1
0
1
1
1
0
1
WSB0#
0
EMAP#
On-Chip Code Memory Map bit
Clear to map the upper 16 Kbytes of on-chip code memory (at FF:4000h-FF:7FFFh) to the data
space (at 00:C000h-00:FFFFh).
Set not to map the upper 16 Kbytes of on-chip code memory (at FF:4000h-FF:7FFFh) to the data
space.
RD1
RD0
P1.7
P3.7/RD#
PSEN#
WR#
External Memory
0
0
A17
A16
Read signal for all external
memory locations
Write signal for all external
memory locations
256 Kbytes
0
1
I/O pin
A16
Read signal for all external
memory locations
Write signal for all external
memory locations
128 Kbytes
1
0
I/O pin
I/O pin
Read signal for all external
memory locations
Write signal for all external
memory locations
64 Kbytes
1
1
I/O pin
Read signal for regions 00:
and 01:
Read signal for regions FE:
and FF:
Write signal for all external
memory locations
2
×
64 Kbytes
(1)
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