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參數(shù)資料
| 型號： | TSC80251-SK |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8/16-bit Microcontroller with Serial Communication Interfaces |
| 中文描述： | 16位產(chǎn)品微控制器的串行通信接口 |
| 文件頁數(shù)： | 31/63頁 |
| 文件大?。?/td> | 878K |
| 代理商： | TSC80251-SK |
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31
Rev. A - May 7, 1999
TSC80251G2D
Figure 9. Setup for Programming
Table 38. Programming Modes
Notes:
1. Signature Bytes are not user-programmable.
2. The ALE/PROG# pulse waveform is shown in Figure 31 page 54.
8.5 Verify Algorithm
Figure 10 shows the hardware setup needed to verify the TSC87251G2D EPROM/OTPROM or TSC83251G2D
ROM areas:
G
The chip has to be put under reset and maintained in this state until the completion of the verifying sequence.
G
PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
G
Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in
this state until the completion of the verifying sequence (see below).
G
The voltage on the EA# pin must be set to V
DD
and ALE must be set to a high level.
G
The Verifying Mode is selected according to the code applied on Port 0. It has to be applied until the completion
of this verifying operation.
G
The verifying address is applied on Ports 1 and 3 which are respectively the MSB and the LSB of the address.
G
Then device is driving the data on Port 2.
G
It is possible to alternate programming and verification operation (see Paragraph 8.4). Please make sure the
voltage on the EA# pin has actually been lowered to V
DD
before performing the verifying operation.
G
PSEN# and the other control signals have to be released to complete a sequence of verifying operations or a
sequence of programming and verifying operations.
ROM Area
(1)
RST
EA#/VPP
PSEN#
ALE/PROG#
(2)
P0
P2
P1(MSB) P3(LSB)
On-chip Code Memory
1
V
PP
0
1 Pulse
68h
Data
16-bit Address
0000h-7FFFh (32 Kbytes)
Configuration Bytes
1
V
PP
0
1 Pulse
69h
Data
CONFIG0: FFF8h
CONFIG1: FFF9h
Lock Bits
1
V
PP
0
1 Pulse
6Bh
X
LB0: 0001h
LB1: 0002h
LB2: 0003h
Encryption Array
1
V
PP
0
1 Pulse
6Ch
Data
0000h-007Fh
VDD
PSEN#
ALE/PROG#
EA#/VPP
XTAL1
VDD
4 to 12 MHz
RST
V
PP
100
μ
s pulses
VSS/VSS1/VSS2
Mode
VDD
A[7:0]
A[14:8]
Data
P0[7:0]
P3[7:0]
P1[7:0]
P2[7:0]
TSC87251G2D
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