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參數資料
| 型號： | TSC21020F-20SCHXXX |
| 廠商： | ATMEL CORP |
| 元件分類： | 數字信號處理外設 |
| 英文描述： | 40-BIT, DSP-FLOATING POINT PROCESSOR, UUC |
| 封裝： | DIE |
| 文件頁數： | 22/37頁 |
| 文件大小： | 483K |
| 代理商： | TSC21020F-20SCHXXX |
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TSC21020F
Rev. E – Oct. 05, 1998
29
Example :
Estimate PEXT with the following assumptions :
D A system with one RAM bank each of PM (48 bits)
and DM (32 bits).
D 32 K × 8 RAM chips are used, each with a load of
10 pF.
D Single-precision mode is enabled so that only 32 data
pins can switch at once.
D PM and DM writes occur every other cycle, with 50 %
of the pins switching.
D The instruction cycle rate is 20 MHz (tCK = 50 ns) and
VDD = 5.0 V.
The PEXT equation is calculated for each class of pins that
can drive :
Pin
Type
#
Pins
%
Switch
×C
×f
×VDD2 PEXT
PMA
PMS
PMWR
PMD
DMA
DMS
DMWR
DMD
15
2
1
32
15
2
1
32
50
0
–
50
0
–
50
68 pF
18 pF
48 pF
18 pF
5 MHz
10 MHz
5 MHz
10 MHz
5 MHz
25 V
0.064 W
0.000 W
0.017 W
0.036 W
0.045 W
0.000 W
0.012 W
0.036 W
PEXT = 0.210 W
A typical power consumption can now be calculated for
this situation by adding a typical internal power
dissipation :
PTOTAL = PEXT + (5 V × IDDIN (typ)) = 0.210 + 1.15
= 1.36 W
Note that the conditions causing a worst case PEXT are
different from those causing a worst case PINT. Maximum
PINT cannot occur while 100 % of the output pins are
switching from all ones to all zeros. Also note that it is not
common for a program to have 100 % or even 50 % of the
outputs switching simultaneously.
Power and Ground Guidelines
To achieve its fast cycle time, including instruction fetch,
data access, and execution, the TSC21020F is designed
with high speed drivers on all output pins. Large peak
currents may pass through a circuit board’s ground and
power lines, especially when many output drivers are
simultaneously charging or discharging their load
capacitances.
These
transient
currents
can
cause
disturbances on the power and ground lines. To minimize
these effects, the TSC21020F provides separate supply
pins for its internal logic (IGND and IVDD) and for its
external drivers (EGND and EVDD).
All GND pins should have a low impedance path to
ground. A ground plane is required in TSC21020F
systems to reduce this impedance, minimizing noise.
The EVDD and IVDD pins should be bypassed to the
ground plane using approximately 14 high-frequency
capacitors (0.1
F ceramic). Keep each capacitor’s lead
and trace length to the pins as short as possible. This low
inductive path provides the TSC21020F with the peak
currents required when its output drivers switch. The
capacitors’ ground leads should also be short and connect
directly to the ground plane. This provides a low
impedance return path for the load capacitance of the
TSC21020F’s output drivers.
If
a
VDD
plane
is
not
used,
the
following
recommendations apply. Traces from the + 5 V supply to
the 10 EVDD pins should be designed to satisfy the
minimum VDD specification while carrying average dc
currents of [IDDEX/10 × (number of EVDD pins per
trace)]. IDDEX is the calculated external supply current. A
similar calculation should be made for the four IVDD pins
using the IDDIN specification. The traces connecting
+ 5 V to the IVDD pins should be separate from those
connecting to the EVDD pins.
A low frequency bypass capacitor (20
F tantalum)
located near the junction of the IVDD and EVDD traces
is also recommended.
Target System Requirements For Use Of
EZ-ICE Emulator
The ADSP-21020 EZ-ICE uses the IEEE 1149.1 JTAG
test access port of the TSC21020F to monitor and control
the target board processor during emulation. The EZ-ICE
probe requires that CLKIN, TMS, TCK, TRST, TDI,
TDO, and GND be made accessible on the target system
via a 12-pin connector (pin strip header) such as that
shown in Figure 20. The EZ-ICE probe plugs directly
onto this connector for chip-on-board emulation ; you
must add this connector to your target board design if you
intend to use the ADSP-21020 EZ-ICE. Figure 21 shows
the dimensions of the EZ-ICE probe ; be sure to allow
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