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參數(shù)資料
| 型號： | TSB43LV81 |
| 英文描述： | IC CYCLONE III FPGA 10K 144 EQFP |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 1/159頁 |
| 文件大?。?/td> | 1085K |
| 代理商： | TSB43LV81 |
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IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
TSB43LV81
SLLS403-December 1999
PRODUCTION DATA information is current
as of publication date. Products conform to
specifications
per
the
Instruments standard warranty. Production
processing does not necessarily include testing
of all parameters.
Page 1
terms
of
Texas
Copy right 1999, Texas Instruments Japan
Fully Interoperable with FireWire
Implementation of IEEE-1394 (1995) and
IEEE1394.a compliant
Interfaces Directly to Texas Instruments
TSB11LV01,TSB21LV03 and TSB41LV0X
Physical Layer Devices (100/200/400 Mbps) by
AUX I/O for more port or Isolation
Single 3.3V Supply Operation with 5V Tolerance
using 5V bias pins.
400M-PHY One port integrated
Automated Read Response for Config-ROM
registers
Automated Single Retry Protocol and Split
Transaction control
Support up to 4 initiators by automated
Transaction and could support more by
firmware(SBP2 Protocol)
Management ORB fetch command/Linked
Command ORB fetch protocol command/Auto
address increment DMA both of direct/indirect
addressing(SBP2 Protocol)
Introduction
Automated PageTable Fetch for DataTransfer
Automated Status Report to Initiator at End of
DMA
8/16Bits asynchronous/synchronous DMA I/F
include SCSI and ATAPI like handshake
Asynchronous Transmit Data automatic
Packetizer DMA/Asynchronous Data Fetch and
dePacketizer DMA(Compliant to SBP2
requirements)
8/16bits Data/Address multiplex Microcontroler
and 8/16bits separated Data/Address bus
3RAM configuration can support High
performance for command exchange and DMA
Asynchronous Command FIFO
: 512 Bytes
Config ROM/LOG FIFO
: 512 Bytes
DMA FIFO
: 4720Bytes
1.
1.1.
Description
The TSB43LV81 provide a high-performance IEEE1394-1995 and IEEE1394.a interface with capability transfer and
receive up to 400Mbps proper-formatted packet. The TSB43LV81 have high-performance internal SBP-2 Protocol
engine, and it can provide high speed ORB exchange between SBP-2 initiators and own node. That means this
TSB43LV81 act as SBP-2 target node. Data packet FIFO has 4096Byte at maximum and Command FIFO has 512Byte at
maximum.
The TSB43LV81 can be used for another purpose such as DPP (Direct Printer Protocol) by address sorting for received
packet. Address filtering for in coming write request packet can correctly sort data packet that sent by peer DPP devices.
Both two protocols could be existing in this TSB43LV81 in same time, and internal ConfigRom CSR can correctly
response for peer Initiator or DPP device.
By above internal high performance feature, external controller can easily make SBP-2 target device and DPP devices.
This document is not intended to serve as tutorial on the 1394, SBP-2, and DPP protocol. User should refer each
documentation.
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