參數(shù)資料
型號: TSB43AA22PDT
英文描述: IC ARRIA GX FPGA 50K 484FBGA
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù): 4/159頁
文件大?。?/td> 1085K
代理商: TSB43AA22PDT
TSB43LV81
IEEE-1394 LINK-LAYER CONTROLLER/400M-PHY ONE-CHIP
Page 4
1.3.3.
MISC
NAME
MODE[1:0]
XRESETP
XRESETL
TM
PIN
29,28
143
111
24
I/O
I
I
I
I
DESCRIPTION
Chip mode select. (NORMAL/PHY/LINK)
Phy reset. Reset for LINK block.
Link reset. Reset for PHY block.
Test mode. Should be Low for all time.
1.3.4.
Physical Layer Port
The Signals in the Physical Layer Interface are defined as follows:
NAME
CPS
TPBIAS
R1
R0
TPB-
TPB+
TPA-
TPA+
X0
XI
FLT1
FLT0
PD
CAN
Contend/LPS
PIN
25
123
127
126
118
119
121
122
139
140
134
133
21
20
22
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I
DESCRIPTION
Cable Power Supply
TPBIAS Output
Current setting resistor
Current setting resistor
Twisted pair cable B negative signal
Twisted pair cable B positive signal
Twisted pair cable A negative signal
Twisted pair cable A positive signal
Crystal oscillator
Crystal oscillator
PLL filter
PLL filter
Power-down input
Cable Not Active output
LPS for PHY Mode, Contend for LINK Mode and Normal
Mode
Note: All Pins in this table are reserved for first sample.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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