參數(shù)資料
型號: TSA5059T
廠商: NXP SEMICONDUCTORS
元件分類: XO, clock
英文描述: 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer
中文描述: PLL FREQUENCY SYNTHESIZER, 2700 MHz, PDSO16
封裝: 3.90 MM, PLASTIC, MS-102, SOT-109-1, SOP-16
文件頁數(shù): 9/24頁
文件大小: 151K
代理商: TSA5059T
1999 Oct 05
9
Philips Semiconductors
Preliminary specification
2.7 GHz I
2
C-bus controlled low phase
noise frequency synthesizer
TSA5059
Reference divider ratio
The reference divider ratio is set by 4 bits in the WRITE
mode, giving 16 different ratios which allow to adjust the
comparison frequency to different values, depending on
the compromise which has to be found between step size
and phase noise.
Table 8 shows the different dividing ratios and the
corresponding comparison frequencies and step size,
assuming the device is provided with a 4 MHz signal at
pin XTAL.
The dividing ratio of 24 is implemented to fulfil the UK-DTT
recommendation regarding offset frequency of
1
6
MHz.
Table 8
Reference dividing ratios
Note
1.
Only valid when the IC is used with a 4 MHz crystal.
Charge pump current
The charge pump current can be chosen from 4 different values depending on the value of bits C1 and C0 in the I
2
C-bus
byte 4, according to Table 9.
Table 9
Charge pump current
R3
R2
R1
R0
RATIO
COMPARISON
FREQUENCY
(1)
STEP
BIT PE = 0
(1)
BIT PE = 1
(1)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
24
5
10
20
40
80
160
320
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
15.625 kHz
166.67 kHz
800 kHz
400 kHz
200 kHz
100 kHz
50 kHz
25 kHz
12.5 kHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
15.625 kHz
166.67 kHz
800 kHz
400 kHz
200 kHz
100 kHz
50 kHz
25 kHz
12.5 kHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
333.33 kHz
1.6 MHz
800 kHz
400 kHz
200 kHz
100 kHz
50 kHz
25 kHz
C1
C0
I
cp
(
μ
A) (absolute value)
MIN.
TYP.
MAX.
0
0
1
1
0
1
0
1
100
210
450
920
135
280
600
1230
170
350
750
1560
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