
43
0992D–BDC–04/09
e2v semiconductors SAS 2009
TS86101G2B
Figure 12-11. DSP Output Clock Implementation (General Case, Values Given for Information Only)
Figure 12-12. DSP Output Clock Implementation (General Case, Values Given for Information Only)
Note:
1. For reference only, MC100EP17 (for a translation to PECL standard level on DSP_CLK) or NBSG16
drivers from On Semiconductor are well-suited to this application.
2. The 100
MUXDAC
VCCD
DGND
10 nF
DSP_CK_T
DSP_CK_F
50
Ω
50
Ω Lines
100
Ω Differential
Load
2.5 K
Ω
GND
3.3V
4 K
Ω
As close as possible to the load
MUXDAC
VCCD
DGND
10 nF
DSP_CK_T
DSP_CK_F
50
Ω
50
Ω Lines
Driver
100
Ω
1 K
Ω
10 nF
GND
1.5V
3.3V
20 K
Ω
HZ