參數(shù)資料
            型號: TS86101G2BVGL
            廠商: E2V TECHNOLOGIES PLC
            元件分類: DAC
            英文描述: PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255
            封裝: HERMETIC SEALED, CERAMIC, BGA-255
            文件頁數(shù): 12/57頁
            文件大小: 1030K
            代理商: TS86101G2BVGL
            2
            0992D–BDC–04/09
            TS86101G2B
            e2v semiconductors SAS 2009
            1.
            Description
            The TS86101G2B is a 10-bit 1.2 Gsps DAC with an integrated 4:1 multiplexer, allowing easy interfacing with standard
            FPGAs. The enhanced linearity and Noise Power Ratio (NPR) performance (9.5 bits equivalent at 1.2 Gsps) over 550 MHz
            instantaneous bandwidth make this product particularly suitable for high-end applications such as arbitrary waveform gen-
            erators and broadband DDS systems.
            2.
            Specifications
            Notes:
            1. Maximum ratings are limiting values only (referenced to GND = 0V), and are to be applied individually, while other parame-
            ters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability. The use of a
            thermal heat sink is mandatory (refer to “Thermal and Moisture Characteristics” on page 36.)
            2. Maximum ratings enable active inputs with MUXDAC power off.
            3. Maximum ratings enable floating inputs with MUXDAC power on.
            Table 2-1.
            Absolute Maximum Ratings
            Parameter
            Symbol
            Comments
            Value
            Unit
            Positive digital power supply
            V
            CCD
            GND to 6.0
            V
            Negative digital power supply
            V
            EED
            –6.0 to GND
            V
            Negative analog power supply
            V
            EEA
            –6.0 to GND
            V
            Maximum difference between negative supply voltages
            V
            EED - VEEA
            0.7
            V
            Digital inputs
            Port Y = A/B/C/D
            <Y0_T; Y9_T> or
            <Y0_F; Y9_F>
            V
            IL > –0.25
            V
            IH < 5.5
            V
            Maximum difference digital inputs
            Port Y = A/B/C/D
            <Y0_T; Y9_T>
            <Y0_F; Y9_F>
            V
            IH - VIL < 1.4
            Vp
            Data ready clock input
            D_CK_T, D_CK_F
            V
            IL > –0.25
            V
            IH < 5.5
            V
            Maximum difference between D_CK_T and D_CK_F
            D_CK_T, D_CK_F
            V
            IH - VIL < 1.4
            Vp
            Master clock input
            CW_IN_T, CW_IN_F
            V
            IL > –3.5
            V
            IH < 0.75
            V
            Maximum difference between CW_IN_T and CW_IN_F
            CW_IN_T, CW_IN_F
            V
            IH - VIL < 1.2
            Vp
            Digital shift select voltage
            CS
            GND to V
            CCD
            V
            Maximum junction temperature
            T
            J
            135
            °C
            Storage temperature
            Tstg
            –65 to 150
            °C
            Lead temperature
            T
            balls
            250 (during 10s max.)
            °C
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