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參數(shù)資料
| 型號(hào)： | TS86101G2BMGS |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255 |
| 封裝： | CI-CGA, 255 PIN |
| 文件頁(yè)數(shù)： | 18/57頁(yè) |
| 文件大?。?/td> | 1030K |
| 代理商： | TS86101G2BMGS |
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25
0992D–BDC–04/09
e2v semiconductors SAS 2009
TS86101G2B
Figure 6-1.
Synchronization of Multiple TS86101G2B Devices
Notes:
1. A counter can be used to determine when the clock can be enabled after power-up.
2. If the clock starts as illustrated below, there is no guarantee that the DACs will start synchronously (they
may start on different edges of the clock). It is essential that the clock starts with clean transitions.
Figure 6-2.
Clock Transition at Power-up
6.3
Programmable DSP Clock
For correct synchronization of the MUXDAC with the DSP/FPGA/ASIC circuit intended to send the digital
data to the MUXDAC, a DSP output clock is provided by the MUXDAC.
To finely synchronize the two devices (MUXDAC and DSP/FPGA/ASIC), a programmable delay can be
applied to the DSP clock. This delay is controlled via the CS_0, CS_1, CS_2 and CS_3 bits and has a
range of 3.1 ns in 200 ps discrete steps.
Please also refer to “Functional Description” on page 20.
The [CS_0;3] bits are TTL signals (1 = TTL high, 10 k
Ω or left open, 0 = TTL low or ground via 10Ω or
less) but can also be implemented as shown in Figure 6-3 on page 26.
VEED / VEEA
Case 1:
CW_IN_T/CW_IN_F
(differential)
0V
90% of VEEA/VEED
-5V
DAC in RESET state
100 ps min
Power up
Clock held high or low
End of reset
Case 2:
CW_IN_T
(single
-
ended)
100 ps min
Clock held high
Case 3:
CW_IN_F
(single
-
ended)
100 ps min
Clock held low
100%
50% of
VEEA/VEED
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