參數(shù)資料
型號： TS86101G2BCGL
廠商： ATMEL CORP
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 10-BIT DAC, PBGA255
封裝： CBGA-255
文件頁數(shù)： 30/57頁
文件大?。?/td> 1119K
代理商： TS86101G2BCGL
36
5343C–BDC–03/06
TS86101G2B
11. Thermal and Moisture Characteristics
Figure 11-1. Simplified Thermal Model for CBGA 255 Package
Notes:
1. Typical values, assuming that the power dissipation is uniform over 25% of the die’s top sur-
face, are extracted from ANSYS thermal simulation.
2. CBGA 255 package is hermetic.
TPD/TOD
Output Propagation Delay
The analog output propagation delay. Measured between the rising edge of the
differential CW_IN clock input (zero crossing point) and the zero crossing point of
a full-scale analog output voltage step. TPD corresponds to one CW_IN clock
cycle pipeline delay plus an internal propagation delay (TOD) including package
access propagation delays and internal (on-chip) delays such as clock input
buffers and DAC conversion times
TSetup
Set-up Time
The time difference between the point of change of the digital input data (zero
crossing of differential input) and the rising edge of the differential data ready input
(zero crossing)
(VSWR)
Voltage Standing Wave Ratio
The VSWR corresponds to the DAC output insertion loss due to output power
reflection. As a reminder, a VSWR of 1.12 corresponds to a 20 dB return loss
(99% power transmitted and 1% reflected) and therefore to a 0.0436 dB
transmission loss
Table 3. Definitions of Terms (Continued)
Abbreviation
Definition
Description
C/Watt
2.2
2.3
= 0.17 W/cm/C
= 0.02 W/cm/C
= 0.17 W/cm/C
= 0.50 W/cm/C
= 0.95 W/cm/C
Top of lid
C/Watt
0.80C/Watt
0.6
0.8C/Watt
4.1
C/Watt
2.6
C/Watt
0.4
0.3
2.8C/Watt
0.9
0.7
0.4
2.3 C/Watt
Silicon Junction
0.20C/Watt
0.4
4.1
0.80
0.6
2.6
0.8
2.8
0.3
2.2
2.3
0.9
0.7
0.4
Silicon Junction
0.20
Silicon
Junction
3.85C/Watt
Ceramic Package
(top half of thickness)
Silicon Die
62.6 mm
2
Cyanate Ester/Ag Glue
Ceramic Package
(bottom half of thickness)
Balls PbSn
Reduction
(result using SPICE, thermal to
electrical equivalent model)
Case where all bottoms of balls
are connected to infinite heat sink:
Infinite heat sink
at bottom of balls
Infinite heat sink
at bottom of balls
Bottom
center of
package
"Around"
center of
package
"Around"
center of
package
Edge
of
package
(bottom of balls
of 4 x 4 array
at center
which are
under die)
(bottom of 48
balls around
die
footprint)
(bottom of
80 balls
around
die footprint)
(bottom of
111 other
balls which
are peripheral)
Assumptions:
square die 7.91 x 7.91 = 62.6 mm
2,
60
m thick Cyanate Ester/Ag glue,
0.85 mm ceramic thickness under die,
Sn63Pb37 balls diameter 0.70 mm,
0.65 mm height under bottom of LGA,
21 x 21 mm CLGA
相關(guān)PDF資料
PDF描述
TS86101G2BVGL SERIAL INPUT LOADING, 10-BIT DAC, PBGA255
TS86101G2BMGS SERIAL INPUT LOADING, 10-BIT DAC, PBGA255
TS86101G2BMGS PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255
TS86101G2BVGL PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255
TS86101G2BCGL PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255
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