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參數(shù)資料
| 型號(hào)： | TS8388BMFSB/QQB3 |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁(yè)數(shù)： | 38/42頁(yè) |
| 文件大小： | 1307K |
| 代理商： | TS8388BMFSB/QQB3 |
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5
Product Specification
TS8388BFS
3.3. ELECTRICAL OPERATING CHARACTERISTICS
VEE = DVEE = -5 V ; VCC = +5 V ; VIN -VINB = 500 mVpp Full Scale differential input ;
Digital outputs 75 or 50
differentially terminated ;
Tj (typical) = 70
°C. Full Temperature Range: up to –55°C<Tc; Tj<+125°C.
Parameter
Symb
Test
level
Min
Typ
Max
Unit
POWER REQUIREMENTS
Positive supply voltage
Analog
Digital (ECL)
Digital (LVDS)
VCC
VPLUSD
1, 2, 6
4
4.7
1.4
5
0
2.4
5.3
2.6
V
Positive supply current
Analog
Digital
ICC
IPLUSD
1, 2
6
1, 2
6
385
395
115
120
445
145
mA
Negative supply voltage
VEE
1, 2, 6
-5.3
-5
-4.7
V
Negative supply current
Analog
Digital
AIEE
DIEE
1, 2
6
1, 2
6
165
170
135
145
200
180
mA
Nominal power dissipation
PD
1, 2
6
3.4
3.6
4.1
4.3
W
Power supply rejection ratio
(note 2)
PSRR
4
0.5
2
mV/V
RESOLUTION
8
bits
ANALOG INPUTS
Full Scale Input Voltage range (differential mode)
( 0 Volt common mode voltage )
VIN
VINB
4
-125
125
mV
Full Scale Input Voltage range (single–ended input option )
(see Application
Notes)
VIN
VINB
4
-250
0
250
mV
Analog input capacitance
CIN
4
3
3.5
pF
Input bias current
IIN
4
10
20
A
Input Resistance
RIN
4
0.5
1
M
Full Power input Bandwidth
FPBW
4
1.3
1.5
GHz
Small Signal input Bandwidth (10 % full scale)
SSBW
4
1.5
1.7
GHz
CLOCK INPUTS
Logic compatibility for clock inputs
(note 10 )
(see Application Notes)
ECL or specified clock input
power level in dBm
ECL Clock inputs voltages (VCLK or VCLKB) :
4
Logic “0” voltage
VIL
-1.5
V
Logic “1” voltage
VIH
-1.1
V
Logic “0” current
IIL
5
50
A
Logic “1” current
IIH
5
50
A
Clock input power level into 50
termination
DBm into 50
Clock input power level
4
-2
4
10
dBm
Clock input capacitance
CCLK
4
3
3.5
pF
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