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參數(shù)資料
| 型號： | TS8388BCF |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 25/44頁 |
| 文件大?。?/td> | 850K |
| 代理商： | TS8388BCF |
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31
Preliminary Beta-Site
Specification
TS8388BF
7.5.
CLOCK SIGNAL DUTY CYCLE ADJUST
At fast sampling rates, ( 1 Gsps and above), the device performance ( especially the SNR ) may be improved by tuning the Clock duty cycle
(CLK,CLKB).
In single ended configuration, when using a sinewave clock generator, the clock signal duty cycle can be easily adjusted by simply offseting the
inphase clock signal using a biasing tee, (as the out of phase clock input is at ground level ).
Single ended Clock input (Inphase clock input common mode shifted)
VCLK common mode = -180mV
VCLKB = 0 Volt
[V]
t
VCLK - 180 mV
VCLKB = ( 0 V )
-0.5V
40 %
60 %
+0.5V
Note 1 : Do not exceed 10 dBm into the 50 ohms termination resistor for single clock input power level.
Note 2 : For an input CLK signal of 4 dBm into 50 ohms, the typical offset value to achieve a 40 / 60 clock duty cycle is -180 mV on CLK.
7.6.
NOISE IMMUNITY INFORMATIONS
Circuit noise immunity performance begins at design level.
Efforts have been made on the design in order to make the device as insensitive as possible to chip environment perturbations resulting from the
circuit itself or induced by external circuitry.
(Cascode stages isolation, internal damping resistors, clamps, internal (onchip) decoupling capacitors.)
Furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced noise immunity by common mode noise
rejection.
Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by these balanced differential amplifiers.
Moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs :
The analog inputs and clock inputs of the TS8388BF device have been surrounded by ground pins, which must be directly connected to the external
ground plane.
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PDF描述 |
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| TS8388BVF | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFB/Q | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMF | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| TS8388BCFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BCG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A/D CONVERTER |
| TS8388BCGL | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BCGL (+LID) | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BMF | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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