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| 型號： | TS80C51RA2-VIA |
| 廠商： | Atmel |
| 文件頁數(shù)： | 14/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 256BYTE 40MHZ 40-DIP |
| 標(biāo)準(zhǔn)包裝： | 9 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40/30MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
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2007-2012 Microchip Technology Inc.
DS70292G-page 23
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
3.0
CPU
3.1
Overview
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 CPU module has
a 16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A
single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any time.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices have
sixteen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a
data, address or address offset register. The 16th
working register (W15) operates as a software Stack
Pointer (SP) for interrupts and calls.
There are two classes of instruction in the
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices: MCU and
DSP. These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 is capable of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1, and
the programmer’s model for the dsPIC33FJ32GP302/
304,
dsPIC33FJ64GPX02/X04,
and
dsPIC33FJ128GPX02/X04 is shown in Figure 3-2.
3.2
Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
3.3
DSP Engine Overview
The DSP engine features a high-speed 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP
instructions operate
seamlessly with
all
other
instructions and have been designed for optimal real-
time performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain working
registers to each address space.
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04,
and
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 2. “CPU” (DS70204) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS80C51RA2-VIAB | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance 8-bit Microcontrollers |
| TS80C51RA2-VIAD | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance 8-bit Microcontrollers |
| TS80C51RA2-VIAR | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance 8-bit Microcontrollers |
| TS80C51RA2-VIB | 功能描述:IC MCU 8BIT 256BYTE 40MHZ 44PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:80C 標(biāo)準(zhǔn)包裝:1,500 系列:AVR® ATtiny 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C，LIN，SPI，UART/USART，USI 外圍設(shè)備:欠壓檢測/復(fù)位，POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):16 程序存儲器容量:8KB（4K x 16） 程序存儲器類型:閃存 EEPROM 大小:512 x 8 RAM 容量:512 x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 11x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:帶卷 (TR) |
| TS80C51RA2-VIBB | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance 8-bit Microcontrollers |
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