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| 型號： | TS80C31X2-LIA |
| 廠商： | Atmel |
| 文件頁數(shù)： | 7/42頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 30/20MHZ 40-DIP |
| 標(biāo)準(zhǔn)包裝： | 9 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 30/20MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | POR |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
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15
4428E–8051–02/08
AT/TS80C31X2
Reset Value = 0000 0000b
Bit addressable
Table 9-3.
SCON Register -- SCON - Serial Control Register (98h)
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
Bit
Mnemonic
Description
7
FE
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
6
SM1
Serial port Mode bit 1
SM0
SM1 Mode Description
Baud Rate
0
Shift Register F
XTAL/12 (/6 in X2 mode)
0
1
8-bit UART
Variable
1
0
2
9-bit UART
F
XTAL/64 or FXTAL/32 (/32, /16 in X2 mode)
1
3
9-bit UART
Variable
5
SM2
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be
cleared in mode 0.
4
REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3
TB8
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2
RB8
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1
TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes.
0
RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 9-2. and Figure 9-3. in the other modes.
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