28
4428E–8051–02/08
AT/TS80C31X2
V
IH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal
oscillator used..
2. Idle I
CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns,
V
IL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 14- 3. Power Down I
CC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC;
XTAL2 NC.; RST = V
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed
on the V
OLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharg-
ing into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus
operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may
exceed 0.45V with maxi V
OL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed
are at room temperature and 5V.
6. Under steady state (non-transient) conditions, I
OL must be externally limited as follows:
Maximum I
OL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If I
OL exceeds the test condition, VOL may exceed the related specification. Pins are not guar-
anteed to sink current greater than the listed test conditions.
7. For other values, please contact your sales office.
8. Operating I
CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL =
IL = VSS + 0.5 V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code
80 FE (label: SJMP label). I
CC would be slightly higher if a crystal oscillator is used. Measure-
ments are made with OTP products when possible, which is the worst case.
Figure 14-1. ICC Test Condition, under reset
EA
VCC
ICC
(NC)
CLOCK
SIGNAL
V
CC
All other pins are disconnected.
RST
XTAL2
XTAL1
V
SS
V
CC
P0