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參數(shù)資料
| 型號(hào)： | TS68HC901CP8 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HCMOS MULTI-FUNCTION PERIPHERAL |
| 中文描述： | HCMOS多功能外設(shè) |
| 文件頁數(shù)： | 25/42頁 |
| 文件大?。?/td> | 369K |
| 代理商： | TS68HC901CP8 |
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0
0
1
1
0
1
0
1
0
1
1
1
0
1
1
1
/
2
2
SYNC
ASYN
C
ASYN
C*
ASYN
C
0
0
1
1
0
1
0
1
8 Bits
7 Bits
6 Bits
5 Bits
(*) : Only used with divide-by-16 clock mode
RECEIVER INTERRUPT CHANNELS
The USART receive section is assigned two inter-
rupt channels. One indicates the buffer full condi-
tion, while the other channel indicates an error
condition. Error conditions include overrun, parity
error, synchronous found, and break. These inter-
rupting conditions correspond to the BF, OE, PE,
and F/S or B bits of the receiver status register.
These flagswill function as described in6.2.2. whe-
ther the receiver interrupt channels are enabled or
disabled.
While only one interrupt is generated per character
received, twodedicated interruptchannelsallowse-
parate vector numbers to be assigned for normal
andabnormal receiver conditions. When a received
word hasan error associated with itand theerrorin-
terrupt channel isenabled, an interruptwill be gene-
rated on theerror channelonly.However, ifthe error
channel is disabled, an interrupt for an error condi-
tion will be generated on the buffer full interrupt
channelalong with interrupts produced by the buffer
full condition. The receiver status register must al-
ways be read to determine which error condition
produced the interrupt.
RECEIVER STATUS REGISTER
The receiver status register contains the receive
buffer fullflag, the synchronous strip enable, there-
ceiver enable, and various status information asso-
ciated with the data word in the receive buffer.The
RSR islatched each timea dataword is transferred
to the receive buffer. RSR flags cannot change a-
gainuntilthedataword hasbeenread.Theexception
is thecharacter in progress flag which monitors when
a new word is being assembled in the asynchronous
character format. The receiver status register is
shown inFigure 18.
SPECIAL RECEIVE CONSIDERATIONS
7
RECEIVER STATUS REGISTER
0
RSR
(2Bh)
BF
OE
PE
FE
F/S or B
M/CIP
SS
RE
CLEARED on RESET
Figure 18 :
Certain receive conditions relating to the overrun error flag and the break defect flag require further ex-
planation. Consider the following examples :
1) Abreak is received while the receive buffer is full. This does not produce an overrun condition. Only
the B flag will be set after the receiver buffer is read.
2) A newword is received and the receive buffer is full. A break is received before the receive buffer is
read.
Both the B and OE flags willbe set when thebuffer full condition is satisfied.
BF
Buffer Full. This bit is set when a received word is transferred to the receivebuffer. This bit
is clearedwhenthe receive buffer isreadby accessing the USART data register (UDR). This
bit is read only.
SET : Received word transferredto buffer
CLEARED : Receive buffer read
OE
Overrun Error. An overrun error occurs when a received word is due to be transferred to the
receive buffer, but the receive buffer is full. Neither the receive buffer nor theRSR is overw-
ritten.The OE bit is set after the receive buffer full condition issatisfied by reading the UDR.
Thiserror condition will generate an interrupt to theprocessor. The OE bit is clearedby rea-
dingthe RSR. New data words will not be assembled until the RSR is read.
TS68HC901
25/42
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PDF描述 |
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| TS68HC901 | HCMOS Multi-Function Peripheral(HCMOS多功能外圍) |
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