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參數(shù)資料
| 型號： | TS68HC901 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HCMOS Multi-Function Peripheral(HCMOS多功能外圍) |
| 中文描述： | HCMOS多功能外設(shè)（HCMOS多功能外圍） |
| 文件頁數(shù)： | 7/42頁 |
| 文件大?。?/td> | 368K |
| 代理商： | TS68HC901 |
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BUSOPERATION
Thefollowingparagraphs explain thecontrolsignals
and bus operation during data transfer operations
and reset.
DATA TRANSFER OPERATIONS.
Transfer ofdata between devices involves the follo-
wing pins: Register Select Bus - RS5 through RS1
DataBus - D0 through D7 Control Signals The ad-
dress and databusesareseparate parallel busesu-
sed to transfer data using an asynchronous bus
structure. In allcycles, the bus master assumes re-
sponsibility fordeskewing allsignals itissues at both
the start and end of a cycle. Additionally, the bus
master is responsible for deskewing the acknow-
ledge and data signals from theperipheral devices.
Read Cycle. To read a CMFP register, CS and DS
must be asserted, and R/W must be high. The
CMFPwill place the content of the register which is
selected by the register select bus (RS1 through
RS5) on the data bus (D1 through D7) and then as-
sert DTACK. The register addresses are shown on
Figure2.Aftertheprocessor has latched thedata, DS
is negated. The negation of either CS or DS will ter-
minate the read operation. The CMFP will drive
DTACKHighandplaceitinthehigh-impedance state.
The timing for a readcycle is shown in figure 21.
Write Cycle.To write a register CS and DS must be
asserted, and R/W must be low. TheCMFP will de-
code theaddress bus to determine which register is
selected. Then the register will be loaded with the
contents of thedata bus and DTACK will be asser-
ted. When the processor recognizes DTACK, DS
will be negated. The write cycleis terminated when
either CS or DS is negated. The CMFP will drive
DTACKhigh andplace itinthehigh-impedance state.
The timing for a write cycle is shown infigure22.
INTERRUPT ACKNOWLEDGE OPERATION.
The CMFP has 16 interrupt sources, eight internal
and eight external. When an interrupt request is
pending, theCMFPwill assertIRQ. In a vectoredin-
terrupt scheme,theprocessor will acknowledge the
interruptrequestbyperforming an interruptacknow-
ledge cycle. IACK and DS will be asserted. The
CMFPresponds totheIACKsignalbyplacing avec-
tor number on the lower eight bits of the data bus.
This vector number corresponds tothe IRQ handler
for the particular interrupt requesting service. The
format of this vector number is given in figure6.
WhentheCMFPasserts DTACKtoindicate that va-
lid dataisonthebus,theprocessor willlatchtheda-
ta and terminate the bus cycle by negating DS.
WheneitherDSorIACKare negated, theCMFPwill
terminate the interrupt acknowledge operation by
driving DTACK high and placing it in thehigh-impe-
dance state. Also, the data bus willbe placed in the
high-impedance state. IRQ will be negated as a re-
sult of the IACK cycle unless additional interrupts
are pending.
The CMFP can be part of a daisy-chain interrupt
structure whichallows multiple CMFPsto be placed
at the same interrupt level by sharing a common
IACK signal. Adaisy-chain priority schemeis imple-
mented with IEI and IEO signals. IEI indicates that
no higher priority device is requesting interrupt ser-
vice. IEO signals lower priority devices that neither
this device nor any higher priority devices is reques-
ting service. To daisy-chain CMFPs, the highest
priority CMFP has its IEI tied low and successive
CMFPs have theirIEI connected to the next higher
priority device’sIEO.Notethatwhenthedaisy-chain
TS68HC901
7/42
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TS68HC901CFN4 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HCMOS MULTI-FUNCTION PERIPHERAL |
| TS68HC901CFN5 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HCMOS MULTI-FUNCTION PERIPHERAL |
| TS68HC901CFN8 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HCMOS MULTI-FUNCTION PERIPHERAL |
| TS68HC901CP4 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HCMOS MULTI-FUNCTION PERIPHERAL |
| TS68HC901CP5 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HCMOS MULTI-FUNCTION PERIPHERAL |
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