參數(shù)資料
型號(hào): TS68HC901
廠商: 意法半導(dǎo)體
英文描述: HCMOS Multi-Function Peripheral(HCMOS多功能外圍)
中文描述: HCMOS多功能外設(shè)(HCMOS多功能外圍)
文件頁(yè)數(shù): 24/42頁(yè)
文件大?。?/td> 368K
代理商: TS68HC901
theuser must determine the synchronous word pa-
rity and write it into synchronous character. The
CMFPwillthen transmit theextra bit in thesynchro-
nous word as a paritybit.
USART CONTROL REGISTER
TheUSART controlregister (UCR)selects the clock
mode and the character format for the receive and
transmit sections. This register is shown in Fig-
ure 17.
RECEIVER
As data is received on the serial input line (SI), it is
clocked into an internal 8-bit shift register until the
specified number ofdatabitshave beenassembled.
Thischaracter willthen be transferred tothe receive
buffer, assuming that the last word in the receiver
buffer hasbeen read. Thistransfer produces a buff-
er full interrupt to the processor.
Reading the receive buffer satisfies the buffer full
condition and allows a next data word to be trans-
ferred to the receive buffer when it is assembled.
The receive buffer is accessed by reading the U-
SART data register (UDR). TheUDRis simply an 8-
bit data register used when transferring data from
the CMFPand CPU.
Each timea word istransferred tothereceive buffer,
its status information islatched into the receiver sta-
tus register (RSR). The RSR is not updated again
until the data word in the receive buffer has been
read. When a buffer full condition exists, the RSR
should always be read before the receive buffer
(UDR) to maintain the correct correspondence be-
tween data and flags. Otherwise, it is possible that
afterreading theUDR and priorto reading the RSR,
a newword could be receiveand transferred to the
7
USART CONTROL REGISTER
0
UCR
(29h)
CLK
WL1
WL0
ST1
ST0
PE
E/O
WU
CLEARED on RESET
Writing 0 : CLEARED
Writing 1 : SET
Figure 17 :
receivebuffer. Its associated flags would be latched into the RSR, over-writing the flagsof theprevious
data word. Then when the RSR were read to access the statusinformation for the first data word, the
flags for the new word wouldbe retrieved.
CLK
Clock Mode. When this bit is zero, data willbe clocked into and outof the receiverand trans-
mitter at the frequency of their respective clocks. When this bit is a one, data will be clocked
into and out of the receiver and transmitter at one sixteenth the frequency of their respective
clocks. Also, the receiver data transition resynchronization logic willbe enabled.
WL0, WL1 Word Length. These two bits specify the length of the data word exclusive of startbits, stop
bits,and parity.
ST0, ST1 Start/Stop Bit and Format Control. These two bits select the number of start and stop bits
and also specify the character format.
PE
Parity Enable. When this bit is zero, no parity check will be made and no parity bit will be
computed for transmission. When this bit is a one, parity will be checked by the receiver and
parity will be calculated and inserted during data transmission. Note that parity is not auto-
matically appended to the synchronous character for word lengths of less than eight bits. In
this case, the parity should be written intothe synchronous character register along with the
synchronous word.
E/0
Even/Odd Parity. When this bit is zero, odd parity is selected. When this bit is a one, even
parity is selected.
WU
Bit 0 Reserved. Must be maintained at 0.
ST1
ST0
Start Bits
Stop Bits
Format
WL1
WL0
Word Length
TS68HC901
24/42
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