參數(shù)資料
型號： TS68EN360VR33L
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-bitQuad Integrated Communication Controller
中文描述： 32-BIT, 33 MHz, RISC PROCESSOR, CPGA241
封裝： CERAMIC, PGA-241
文件頁數(shù)： 64/82頁
文件大?。?/td> 874K
代理商： TS68EN360VR33L
64
TS68EN360
2113A–HIREL–03/02
Notes:
1. SyncCLK/RCLK1andSyncCLK/TCLK1mustbegreaterorequalto2.25/1
2. SDACKisassertedwhenevertheSDMAwritestheincomingframeDAintomemory.
Figure58.
EthernetCollisionTiming
EthernetElectricalSpecifications
GND=0V
dc
,T
C
=-55to+125
°
C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure58toFigure63).
Number
Characteristic
25.0MHz
33.34MHz
Unit
Min
Max
Min
Max
120
CLSNWidthHigh
40
-
40
-
ns
121
RCLK1Rise/FallTime
-
15
-
15
ns
122
RCLK1WidthLow
CLKO1+
5ns
-
CLKO1+
5ns
-
123
(1)
RCLK1WidthHigh
CLKO1
-
CLKO1
-
124
RXD1SetupTime
20
-
20
-
ns
125
RXD1HoldTime
5
-
5
-
ns
126
RENAActiveDelay(fromRCLK1risingedgeofthelast
databit)
10
-
10
-
ns
127
RENAWidthLow
100
-
100
-
ns
128
TCLK1Rise/FallTime
-
15
-
15
ns
129
TCLK1WidthLow
CLKO1+
5ns
-
CLKO1+
5ns
-
130
(1)
TCLK1WidthHigh
CLKO1
-
CLKO1
-
131
TXD1ActiveDelay(fromTCLK1risingedge)
10
50
10
50
ns
132
TXD1InactiveDelay(fromTCLK1risingedge)
10
50
10
50
ns
133
TENAActiveDelay(fromTCLK1risingedge)
10
50
10
50
ns
134
TENAInactiveDelay(fromTCLK1risingedge)
10
50
10
50
ns
135
RSTRTActiveDelay(fromTCLK1fallingedge)
10
50
10
50
ns
136
RSTRTInactiveDelay(fromTCLK1fallingedge)
10
50
10
50
ns
137
RRJCTWidthLow
1
-
1
-
CLKO1
138
(2)
CLKO1LowtoSDACKAsserted
-
20
-
20
ns
139
(2)
CLKO1LowtoSDACKNegated
-
20
-
20
ns
CLSN (CTS1)
(INPUT)
120
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