參數(shù)資料
型號: TS68EN360VR33L
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 32-bitQuad Integrated Communication Controller
中文描述: 32-BIT, 33 MHz, RISC PROCESSOR, CPGA241
封裝: CERAMIC, PGA-241
文件頁數(shù): 39/82頁
文件大?。?/td> 874K
代理商: TS68EN360VR33L
39
TS68EN360
2113A–HIREL–03/02
Note:
1. BGremainslowuntileithertheSDMAortheIDMArequeststheexternalbus.
Figure29.
TS68040CompanionModeArbitration
Notes:
1. TS68040TransferAttributeSignals=SIZx,TTx,TMx,R/W,LOCK.
2. BGalwaysremainsasserteduntileithertheSDMAortheIDMArequeststheexternalbus.
040BusTypeSlaveModeBusArbitrationACElectricalSpecifications
GND=0V
dc
,T
C
=-55to+125
°
C.Theelectricalspecificationsinthisdocumentarepreliminary(SeeFigure29).
Number
Characteristic
25.0MHz
33.34MHz
Unit
Min
Max
Min
Max
231
Address,TransferAttributesHighImpedancetoClockHigh
7
-
6
-
ns
232
(1)
ClockHightoBGLow
-
20
-
15
ns
233
ClockHightoBGHigh
4
20
4
15
ns
234
BBHightoClockHigh(040output)
7
-
6
-
ns
235
BBHighImpedancetoClockHigh(040output)
0
-
0
-
ns
236
ClockHightoBBLow(360Output)
-
20
-
15
ns
237
ClockHightoBBHigh(360Output)
-
20
-
15
ns
238
ClockLowtoBBHighImpedance(360output)
-
20
-
15
ns
(OUTPUT)
BCLRO
BG
(OUTPUT)
BB
(I/O)
A31-A0
(I/O)
CLKO1
(OUTPUT)
TRANSFER
ATTRIBUTES
(INPUT)
(INPUT)
BCLRI
S0
S1
S2
S3
S4
S5
C2
C1
238
040 BUS MASTER
360 BUS MASTER
60
61
237
234
231
233
232
235
140
141
236
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