參數(shù)資料
型號： TS68EN360MR33L
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-bitQuad Integrated Communication Controller
中文描述： 32-BIT, 33 MHz, RISC PROCESSOR, CPGA241
封裝： CERAMIC, PGA-241
文件頁數(shù)： 7/82頁
文件大?。?/td> 874K
代理商： TS68EN360MR33L
7
TS68EN360
2113A–HIREL–03/02
BusControl
DataandSize
Acknowledge
DSACK1-DSACK0
Providesasynchronousdatatransferacknowledgementand
dynamicbussizing(open-drainI/Obutdrivenhighbefore
three-stated).
AddressStrobe
AS
Indicatesthatavalidaddressisontheaddressbus.(I/O)
DataStrobe
DS
Duringareadcycle,DSindicatesthatanexternaldevice
shouldplacevaliddataonthedatabus.Duringawritecycle,
DSindicatesthatvaliddataisonthedatabus.(I/O)
Size
SIZ1-SIZ0
Indicatesthenumberofbytesremainingtobetransferredfor
thiscycle.(I/O)
Read/Write
R/W
Indicatesthedirectionofdatatransferonthebus.(I/O)
OutputEnableAddress
Multiplex
OE/AMUX
Activeduringareadcycleindicatesthatanexternaldevice
shouldplacevaliddataonthedatabus(O)orprovidesa
strobeforexternaladdressmultiplexinginDRAMaccesses
ifinternalmultiplexingisnotused.(O)
Interrupt
Control
InterruptRequest
Level 7-1
IRQ7-IRQ1
ProvidesexternalinterruptrequeststotheCPU32+at
prioritylevels7-1.(I)
Autovector/Interrupt
Acknowledge5
AVEC/IACK5
Autovectorrequestduringaninterruptacknowledgecycle
(open-drainI/O)orinterruptlevel5acknowledgeline.(O)
System
Control
SoftReset
RESETS
Softsystemreset.(open-drainI/O)
HardReset
RESETH
Hardsystemreset.(open-drainI/O)
Halt
HALT
Suspendsexternalbusactivity.(open-drainI/O)
BusError
BERR
Indicatesanerroneousbusoperationisbeingattempted.
(open-drainI/O)
ClockandTest
SystemClockOut1
CLKO1
Internalsystemclockoutput1.(O)
SystemClockOut2
CLKO2
Internalsystemclockoutput2-normally2xCLKO1.(O)
CrystalOscillator
EXTAL,XTAL
Connectionsforanexternalcrystaltotheinternaloscillator
circuit.EXTAL(I),XTAL(O).
ExternalFilterCapacitor
XFC
Connectionpinforanexternalcapacitortofilterthecircuitof
thePLL.(I)
ClockModeSelect1-0
MODCK1-MODCK0
Selectsthesourceoftheinternalsystemclock.(I)THESE
PINSSHOULDNOTBESETTO00
InstructionFetch/
DevelopmentSerialInput
IFETCH/DSI
IndicateswhentheCPU32+isperforminganinstruction
wordprefetch(O)orinputtotheCPU32+backgrounddebug
mode.(I)
InstructionPipe0/
DevelopmentSerial
Output
IPIPE0/DSO
Usedtotrackmovementofwordsthroughtheinstruction
pipeline(O)oroutputfromtheCPU32+backgrounddebug
mode.(O)
InstructionPipe1/Row
AddressSelect1
Double-Drive
IPIPE1/RAS1DD
Usedtotrackmovementofwordsthroughtheinstruction
pipeline(O),orarowaddressselect1“double-drive”output
(O).
Breakpoint/Development
SerialClock
BKPT/DSCLK
SignalsahardwarebreakpointtotheQUICC(open-drain
I/O),orclocksignalforCPU32+backgrounddebugmode(I).
Freeze/Initial
Configuration2
FREEZE/CONFIG2
IndicatesthattheCPU32+hasacknowledgedabreakpoint
(O),orinitialQUICCconfigurationselect(I).
Table1.
SystemBusSignalIndex(NormalOperation)(Continued)
Group
SignalName
Mnemonic
Function
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參數(shù)描述
TS68EN360MRB/C25L 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:32-bitQuad Integrated Communication Controller
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TS68EN360MRBQ25L 制造商:e2v technologies 功能描述:5962-97671MXC - Trays 制造商:e2v technologies 功能描述:INTEGRATED COMMUNICATION PROCESSOR 241CPGA - Rail/Tube
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