參數(shù)資料
型號: TS68C429AMF
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT
中文描述: 3 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, CQFP132
封裝: CERAMIC, QFP-132
文件頁數(shù): 23/43頁
文件大小: 1638K
代理商: TS68C429AMF
23
TS68C429A
2120A–HIREL–08/02
The transmission frequency can be computed by dividing the CLK ARINC frequency by
the frequency register value.
The frequency register must be loaded with a value greater or equal to 2.
The Transmitter Control Register
The transmitter control register is accessible for reading and writing operations.
Figure 18.
Transmitter Control Register
Table 10.
Transmission Control Register Description
Bit
Function
Comments
Bit 15
Enable transmission
- 0: channel out of service (stops on going transmission)
- 1: channel in service
- 1 to 0: transition is not allowed at the same time as an 1 to 0 transition of the bit 4
- when the transmitter FIFO is empty and when no transmission is on going, the first
write access to the FIFO has to be preceded by the following sequence: reset to 0
and then set to 1
Bit 14
Test (only 3rd channel)
0: normal operating
1: test, output are only driven on internal lines for input testing
Bit 13 to 12
Not used
Bus 11
Parity control
0: even parity calculation
1: odd parity calculation
Bit 10
Parity control
0: parity disable, Bit 32 of the message stays unchanged
1: parity enable. Bit 32 of the message will be forced by parity control
Bit 9 to 5
Transmission gap
“transmission gap” which is the delay between two 32-bit ARINC messages (in
ARINC bit)
Bit 4
Reset FIFO
- write a 0 in this bit reset the FIFO counter
- this bit must be set to 1 before any write in the transmit buffer.
- 1 to 0: transition is not allowed at the same time as an 1 to 0 transition of the bit 15
Bit 3 to 0
Number of msg
these four bits indicate the available space within the FIFO
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