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參數(shù)資料
| 型號(hào)： | TRF5001GQE |
| 英文描述： | RECEIVER|BICMOS|BGA|80PIN|PLASTIC |
| 中文描述： | 接收機(jī)| BICMOS工藝| BGA封裝| 80腳|塑料 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 258K |
| 代理商： | TRF5001GQE |
DATE AND TRACKING INFORMATION
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DSPCLK
Internal or External
Analog Input
ADC Output
= Sample point
tDSPCLK = 1/Fsample
tDSPCLK
tHOLD
tSETUP
tD
tHOLD = 0.5* tDSPCLK
tSETUP = 0.5* tDSPCLK - tD
tD =
～
10 nsec
N-1
N-2
Figure 2. ADC Timing Diagram
power-up/-down time
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μ
s
μ
s
Power-up time (excludes PLL/VCO components)
Output power within 10% of steady-state values
100
Power-down time
100
timing requirements, serial data interface (see Figure 3)
PARAMETER
MIN
NOM
MAX
UNIT
f(CLOCK)
t(HIGH)
tf
tr
t(LOW)
t(START)
t(END)
t(SUDA)
t(HDDA)
t(STHIGH)
Clock frequency
20
MHz
Clock hold time
20
ns
Clock fall time
8
ns
Clock rise time
8
ns
Clock low time
20
ns
Delay to rising clock edge
10
20
ns
Delay from falling edge of clock to rising edge of strobe
20
ns
DATA setup time
20
ns
DATA hold time
20
ns
Minimum EN pulse hold time
40
ns
Clock duty cycle
40
50
60
%
P
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