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參數(shù)資料
| 型號： | TRCV012G7 |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer |
| 中文描述： | TRCV012G5（2.5 Gb /秒）和TRCV012G7（2.5 Gb /秒和2.7 Gb /秒）限幅放大器，時鐘恢復(fù)，1:16數(shù)據(jù)復(fù)用器 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 500K |
| 代理商： | TRCV012G7 |
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TRCV012G5 and TRCV012G7
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet
August 2000
14
Lucent Technologies Inc.
Clock and Data Recovery (CDR)
(continued)
Data Path Configuration Option (ENDATAN)
Either the limiting amplifier (LAINP/N) or a CML logic level input (DATAP/N) can be selected as the source of the
2.5 Gbits/s data signal. The DATAP/N input can be used if the limiting amplifier is not needed, or it can be used as
a system loopback path when the limiting amplifier is the normal data path. If the limiting amplifier is not used in
normal operation, the LAINP/N pins should be grounded through a series ac coupling of 0.1
μ
F.
High-Speed Serial Clock and Data Output Enables (ENCK2G5N, END2G5N)
Separate output enables are provided for the 2.5 GHz recovered clock output (CK2G5P/N) and the 2.5 Gbits/s
data output (D2G5P/N). These enables are active-low CMOS inputs with internal pull-up resistors. A ground or
logic low applied to the pin enables the corresponding output. When disabled, the pins should be either left floating,
or be connected to a load which returns to V
CC
. The high-speed serial clock and data outputs must not be con-
nected directly to ground when they are disabled.
High-Speed Serial Data Output Mute (MUTE2G5N)
The 2.5 Gbits/s data output (D2G5P/N) may be forced to a logic-low state using MUTE2G5N. This may be desir-
able if the quality of the input data is suspect, as may be the case under LOSA or LOSD conditions. MUTE2G5N is
an active-low CMOS input.
Data and CDR Configuration Options (REFSELN, INLOSN, MUTEDMXN)
A 155 MHz clock (REFCLKP/N) may optionally be provided as a frequency reference to the clock recovery PLL in
order to control the recovered clock frequency when data timing is lost, as may be the case under LOSA or LOSD
conditions. If REFCLKP/N is provided, REFSELN can be used to select REFCLKP/N as the frequency reference to
the clock recovery PLL.
The INLOSN pin will force the VCO to decrease to its minimum frequency. This will prevent the VCO frequency
from drifting to a high value during invalid signal conditions. INLOSN may be used to limit the recovered clock fre-
quency in systems that do not provide a REFCLKP/N signal.
The MUTEDMXN pin will force logic-low data into the demultiplexer, and therefore, keep all demultiplexer outputs
in the logic-low state. MUTEDMXN will not affect the operation of the CDR circuits. This may be desirable if the
quality of the input data is suspect as may be the case under LOSA or LOSD conditions.
The user may utilize the REFSELN, INLOSN, and MUTEDMXN pins in any combination to achieve the desired
response under LOS conditions.
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| TRCV012G5 | Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer(2.5 Gbits/s)(限幅放大器，時鐘恢復(fù)，1：16數(shù)據(jù)多路分解器(2.5 G位/秒)) |
| TRCV012G7 | Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer(2.5 Gbits/s and 2.7 Gbits/s)(限幅放大器，時鐘恢復(fù)，1：16數(shù)據(jù)多路分解器(2.5 G位/秒和 2.7 G位/秒)) |
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相關(guān)代理商/技術(shù)參數(shù) |
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