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參數(shù)資料
| 型號： | TRCV012G73XE1 |
| 元件分類： | 運動控制電子 |
| 英文描述： | TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer |
| 中文描述： | TRCV012G5（2.5 Gb /秒）和TRCV012G7（2.5 Gb /秒和2.7 Gb /秒）限幅放大器，時鐘恢復，1:16數(shù)據(jù)復用器 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 500K |
| 代理商： | TRCV012G73XE1 |
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TRCV012G5 and TRCV012G7
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Preliminary Data Sheet
August 2000
8
Lucent Technologies Inc.
Pin Information
(continued)
Table 2. Pin Descriptions—155.52 Mbits/s and Related Signals
(continued)
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
I = input, O = output. I
u
= an internal pull-up resistor on this pin, I
d
= an internal pull-down resistor on this pin, I
t
= an internal termination resis-
tance of 50
on this pin.
Pin
115
Symbol
*
PDDMXN
Type
I
u
Level
CMOS
Name/Description
Powerdown Demultiplexer Circuit (Active-Low).
0 = demultiplexer powered off, D[15:0]P/N and PARITYP/N
are high-impedance
1 or no connection = demultiplexer powered on
Mute Data to Demultiplexer Circuit (Active-Low).
0 = mute data
1 or no connection = normal data
Recovered Clock Output (155 MHz).
155 MHz recovered differential clock output. Pins are active
but forced to differential logic low when MUTE155N = 0.
Mute CK155P/N Clock Output (Active-Low).
Forces
CK155P/N to logic low when MUTE155N is active.
0 = muted
1 or no connection = enabled
Parity Input Over Data (D[15:0]).
Active only when
PDDMXN = 1.
Reference Clock Input (155 MHz).
This clock is optional. If
applying the REFCLKP/N, set the REFCLKP/N to one of
the following frequencies:
117
MUTEDMXN
I
u
CMOS
108
107
CK155P
CK155N
O
LVPECL
114
MUTE155N
I
u
CMOS
105
104
111
110
PARITYP
PARITYN
REFCLKP
REFCLKN
O
LVPECL
I
LVPECL
I
155.52 MHz if using the TRCV012G5, or the
TRCV012G7 at the 0C-48/STM-16 rate of 2.48832 GHz.
I
166.62 MHz if using the TRCV012G7 at the RS FEC
0C-48/STM-16 rate of 2.66606 GHz.
Reference Select to PLL.
Selects LAINP/N or DATAP/N, or
REFCLKP/N as the input to the CDR PLL.
0 = select REFCLKP/N
1 or no connection = select LAINP/N or DATAP/N
113
REFSELN
I
u
CMOS
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PDF描述 |
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| TRCV012G5 | TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer |
| TRCV012G7 | TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer |
| TRCV012G5 | Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer(2.5 Gbits/s)(限幅放大器，時鐘恢復，1：16數(shù)據(jù)多路分解器(2.5 G位/秒)) |
| TRCV012G7 | Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer(2.5 Gbits/s and 2.7 Gbits/s)(限幅放大器，時鐘恢復，1：16數(shù)據(jù)多路分解器(2.5 G位/秒和 2.7 G位/秒)) |
| TRR1Axxx | Miniature, cost-efective switching solution,,state of the art capsule designs |
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