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參數(shù)資料
| 型號： | TR1003 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 111K |
| 代理商： | TR1003 |
Pin
Name
Description
15
PWIDTH
The PWIDTH pin sets the width of the ON pulse to the first RF amplifier t
PW1
with a resistor R
PW
to ground (the ON
pulse width to the second RF amplifier t
PW2
is set at 1.1 times the pulse width to the first RF amplifier). The ON
pulse width t
PW1
can be adjusted between 0.55 and 1 μs with a resistor value in the range of 200 K to 390 K. The
value of R
PW
is given by:
R
PW
= 404* t
PW1
- 18.6, where t
PW1
is in μs and R
PW
is in kilohms
A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifi-
ers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier
ON times are controlled by the PRATE resistor as described above. It is important to keep the total capacitance
between ground, Vcc and this node to less than 5 pF to maintain stability. When using the high data rate operation
with the sleep mode, connect the 1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the
sleep mode.
16
VCC2
VCC2 is the positive supply voltage pin for the receiver RF section and transmitter oscillator. Pin 16 must be by-
passed with an RF capacitor, and must also be bypassed with a 1 to 10 μF tantalum or electrolytic capacitor. See
the
ASH Transceiver Designer’s Guide
for additional information.
17
CNTRL1
CNTRL1 and CNTRL0 select the receive and transmit modes. CNTRL1 and CNTRL0 both high place the unit in
the receive mode. CNTRL1 high and CNTRL0 low place the unit in the ASK transmit mode. CNTRL1 low and
CNTRL0 high place the unit in the OOK transmit mode. CNTRL1 and CNTRL0 both low place the unit in the
power-down (sleep) mode. CNTRL1 is a high-impedance input (CMOS compatible). An input voltage of 0 to
300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is interpreted as a logic high. An
input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum
source current of 40 μA. A logic low requires a maximum sink current of 25 μA (1 μA in sleep mode). This pin
must be held at a logic level; it cannot be left unconnected. At turn on, the voltage on this pin and CNTRL0 should
rise with Vcc until Vcc reaches 2.7 Vdc (receive mode). Thereafter, any mode can be selected.
18
CNTRL0
CNTRL0 is used with CNTRL1 to control the receive and transmit modes of the transceiver. CNTRL0 is a
high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input
voltage of Vcc - 300 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV
should not be applied to this pin. A logic high requires a maximum source current of 40 μA. A logic low requires a
maximum sink current of 25 μA (1 μA in sleep mode). This pin must be held at a logic level; it cannot be left un-
connected. At turn on, the voltage on this pin and CNTRL1 should rise with Vcc until Vcc reaches 2.7 Vdc (receive
mode). Thereafter, any mode can be selected.
19
GND3
GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.
20
RFIO
RFIO is the RF input/output pin. This pin is connected directly to the SAW filter transducer. Antennas presenting
an impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series match-
ing coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three
components. For some impedances, two inductors and a capacitor will be required. A DC path from RFIO to
ground is required for ESD protection.
11
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