參數(shù)資料
型號(hào): TPS7330Q
廠商: Texas Instruments, Inc.
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
中文描述: 低技術(shù),集成延遲復(fù)位功能降穩(wěn)壓器
文件頁數(shù): 30/43頁
文件大?。?/td> 638K
代理商: TPS7330Q
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 32
30
10
0
R
40
50
f – Frequency – Hz
RIPPLE REJECTION
vs
FREQUENCY
60
20
10
100
1 K
10 K
100 K
1 M
10 M
TA = 25
°
C
No Input
Capacitance Added
VI = VO + 1 V
IO = 100 mA
Co = 4.7
μ
F (CSR = 1)
TPS7333
TPS7301 With
VO Programmed
to 2.5 V
TPS7348/
TPS7350
Figure 33
10
100
1 k
10 k
100 k
Co = 10
μ
F (CSR = 1
)
Co = 4.7
μ
F (CSR = 1
)
Co = 100
μ
F (CSR = 1
)
f – Frequency – Hz
OUTPUT SPECTRAL-NOISE DENSITY
vs
FREQUENCY
10
1
0.1
0.01
TA = 25
°
C
No Input Capacitance Added
VI = VO + 1 V
O
V
μ
Figure 34
0.1
0.01
0
50
100
150
200
250
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)
vs
OUTPUT CURRENT
100
Region of Instability
10
IO – Output Current – mA
C
Region of Instability
1
TA = 25
°
C
VI = VO + 1 V
Co = 4.7
μ
F
No Added Ceramic Capacitance
No Input Capacitance Added
Figure 35
0.1
0.01
0
0.1
0.2
Added Ceramic Capacitance –
μ
F
0.3
0.4
0.5
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)
vs
ADDED CERAMIC CAPACITANCE
100
TA = 25
°
C
VI = VO + 1 V
IO = 500 mA
Co = 4.7
μ
F
No Input Capacitor Added
10
0.6
0.7 0.8
0.9
1
1
Region of Instability
Region of
Instability
C
相關(guān)PDF資料
PDF描述
TPS7330Y LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
TPS7333Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
TPS7348Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
TPS7333Y LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
TPS7325Y LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
相關(guān)代理商/技術(shù)參數(shù)
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