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參數(shù)資料
| 型號： | TPS65150RGE |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Low Input Voltage, Compact LCD Bias IC With VCOM Buffer |
| 中文描述： | 低輸入電壓，緊湊型LCD偏置集成電路VCOM緩沖器 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 1126K |
| 代理商： | TPS65150RGE |
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www.ti.com
TPS65150
SLVS576–SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.3 V, Vs = 10 V, T
A
= –40
°
C to 85
°
C, typical values are at T
A
= 25
°
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CTRL = GND, VGH = open
CTRL = GND, VGH = open
I
OUT
= 20 mA
I
DRP
= 50 mA,
V
FBP
= V
FBPNominal
– 5%
I
DRP
= 100 mA,
V
FBP
= V
FBPNominal
– 5%
VGH=24V, Iload=0mA to 20mA
MIN
1.187
TYP
1.214
MAX
1.238
100
UNIT
V
nA
V
FB
I
FB
R
DS(on)
Feedback regulation voltage
Feedback input bias current
Q3 P-Channel switch RDSon
10
1.1
420
650
V
DropN
Current sink voltage drop
(1)
mV
900
1400
Load regulation
0.07
%/mA
VGH ISOLATION SWITCH, GATE VOLTAGE FALL TIME CONTROL
R
DS(on)
Q5 - Pass MOSFET R
DSon
Iadj
Capacitor charge current
Minimum output voltage
I
VGH
Maximum output current
TIMING CIRCUITS DLY1, DLY2, FDLY
I
DLY1
Drive current into delay capacitor DLY1
I
DLY2
Drive current into delay capacitor DLY1
R
FDLY
Fault time delay resistror
(2)
GATE DRIVE (GD)
V
(GD, Vs)
Gate drive threshold
(3)
I
OUT
= 20 mA
Vadj = 20 V, CPI = 30 V
Vadj = 0 V, I
VGH
= 10 mA
12
30
μA
V
mA
160
200
240
2
20
V
DLY1
= 1.213 V
V
DLY2
= 1.213 V
3
3
5
5
7
7
μA
μA
k
250
450
650
Vs rising
–12% of
–4% of
V
Vs
Vs
0.5
V
OL
I
LKG
Vcom Buffer
V
CM
V
os
Gate drive output low voltage
Gate drive output leakage current
I
(sink)
= 500 μA
V
GD
= 15 V
V
μA
0.001
1
Common mode input range
Input offset voltage
2.25
–25
–37
–77
–85
–110
–300
1.2
0.65
0.15
(Vs) –2V
V
I
OUT
= 0 mA
Io =
±
25 mA
Io =
±
50 mA
Io =
±
100 mA
Io =
±
150 mA
25
37
55
85
mV
DC load regulation
mV
110
300
I
B
I
peak
VCOMIN Input bias current
Peak output current
–30
nA
Vs = 15 V
Vs = 10 V
Vs = 5 V
A
(2)
(3)
The fault time is calculated as: t
= C
×
R = C
×
450 k
The GD signal is latched low when the main boost converter output Vs is within regulation. The GD signal is reset when the input
voltage or enable of the boost converter is cycled low.
4
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