參數(shù)資料
型號: TPS65021RHARG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 3-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC40
封裝: 6 X 6 MM, GREEN, PLASTIC, MO-220/VJJD-2, QFN-40
文件頁數(shù): 18/47頁
文件大?。?/td> 1180K
代理商: TPS65021RHARG4
www.ti.com
SYSTEM RESET + CONTROL SIGNALS
DEFLDO1 and DEFLDO2
Interrupt Management and the INT Pin
SLVS613B – OCTOBER 2005 – REVISED JULY 2007
The RESPWRON signal can be used as a global reset for the application. It is an open drain output. The
RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for
tnrespwron seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by
an external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by
the HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms.
The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and
LOWBAT_SNS input signals. Each input signal is compared to a 1 V threshold (falling edge) with 5% (50 mV)
hysteresis.
The DCDC3 converter is reset to its default output voltage defined by the DEFDCDC3 input, when HOT_RESET
is asserted. Other I2C registers are not affected. Generally, the DCDC3 converter is set to its default voltage with
one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout
(UVLO) condition, RESPWRON active, both DCDC3-converter AND DCDC1-converter disabled. In addition, the
voltage of VDCDC3 changes to 1xxx0, if the VDCDC1 converter is disabled. Where xxx is the state before
VDCDC1 was disabled.
These two pins are used to set the default output voltage of the two 200 mA LDOs. The digital value applied to
the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of
both LDOs can be changed during operation with the I2C interface as described in the interface description.
Table 3.
DEFLDO2
DEFLDO1
VLDO1
VLDO2
0
1.1 V
1.3 V
0
1
1.5 V
1.3 V
1
0
2.6 V
2.8 V
1
3.15 V
3.3 V
The INT pin combines the outputs of the PGOOD comparators from each dc-dc converter and LDOs. The INT
pin is used as a POWER_OK pin indicating when all enabled supplies are in regulation. If the PGOODZ register
is read via the serial interface, any active bits are then blocked from the INT output pin.
Interrupts can be masked using the MASK register; default operation is not to mask any DCDC or LDO
interrupts since this provides the POWER_OK function.
25
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