參數(shù)資料
型號: TPS65014RGZ
廠商: Texas Instruments, Inc.
英文描述: POWER AND BATTERY MANAGEMENT IC FOR LI-ION POWERED SYSTEMS
中文描述: 電源和電池管理集成電路鋰離子供電系統(tǒng)
文件頁數(shù): 48/53頁
文件大?。?/td> 1021K
代理商: TPS65014RGZ
www.ti.com
MASK3 Register (Address: 0Fh—Default Value: 00h)
DEFGPIO Register Address: (10h—Default Value: 00h)
TPS65014
SLVS551–DECEMBER 2004
Bit 3-Bit 2 - The function of the LDO1 enable and LDO1 OFF / nSLP bits is shown in the following table. See the
power-on sequencing section for details of low-power mode. Note that programming LDO1 to a higher voltage
may force a system power-on reset if the increase is in the 10% or greater range.
LDO1 ENABLE
0
1
1
LDO1 OFF / nSLP
X
0
1
LDO STATUS IN NORMAL MODE
OFF
ON, full power
ON, full power
LDO STATUS IN LOW-POWER MODE
OFF
ON, reduced power/performance
OFF
Bit 1-Bit 0 - LDO1<1:0>: The LDO1 output voltage is per default set externally. If so desired, this can be changed
via the serial interface.
LDO11
0
0
1
1
LDO10
0
1
0
1
VLDO1
ADJ
2.5 V
2.75 V
3.0 V
MASK3
B7
B6
B5
B4
B3
B2
B1
B0
Edge trigger
GPIO4
0
R/W
Edge trigger
GPIO3
0
R/W
Edge trigger
GPIO2
0
R/W
Edge trigger
GPIO1
0
R/W
Bit name
Mask GPIO4
Mask GPIO3
Mask GPIO2
Mask GPIO1
Default
Read/write
0
0
0
0
R/W
R/W
R/W
R/W
The MASK3 register must be considered when any of the GPIO pins are programmed as inputs.
Bit 7-Bit 4 - Edge trigger GPIO<4:1>: determine whether the respective GPIO generates an interrupt at a rising or
a falling edge.
0 = falling edge triggered.
1 = rising edge triggered.
Bit 3-Bit 0 - Mask GPIO<4:1>: can be used to mask the corresponding interrupt. Default is unmasked (mask
GPIOx = 0).
DEFGPIO
Bit name
Default
Read/write
B7
IO4
0
R/W
B6
IO3
0
R/W
B5
IO2
0
R/W
B4
IO1
0
R/W
B3
B2
B1
B0
Value GPIO4
0
R/W
Value GPIO3
0
R/W
Value GPIO2
0
R/W
Value GPIO1
0
R/W
The DEFGPIO register is used to define the GPIO pins to be either input or output.
Bit 7-Bit 4 - IO<4:1>:
0 = sets the corresponding GPIO to be an input.
1 = sets the corresponding GPIO to be an output.
Bit 3-Bit 0 - Value GPIO<4:1>: If a GPIO is programmed to be an output, then the signal output is determined by
the corresponding bit. The output circuit for each GPIO is an open-drain NMOS requiring an external pullup
resistor.
1 = activates the relevant NMOS, hence forcing a logic low signal at the GPIO pin.
0 = turns the open-drain transistor OFF, hence the voltage at the GPIO pin is determined by the voltage to
which the pullup resistor is connected.
If a particular GPIO is programmed to be an input, then the contents of the relevant bit in B3-0 is defined by the
logic level at the GPIO pin. A logic low forces a
0
and a logic high forces a
1
. If a GPIO is programmed to be an
input, then any attempt to write to the relevant bit in B3-0 is ignored.
48
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