參數(shù)資料
型號(hào): TPS65014RGZ
廠商: Texas Instruments, Inc.
英文描述: POWER AND BATTERY MANAGEMENT IC FOR LI-ION POWERED SYSTEMS
中文描述: 電源和電池管理集成電路鋰離子供電系統(tǒng)
文件頁數(shù): 47/53頁
文件大?。?/td> 1021K
代理商: TPS65014RGZ
www.ti.com
VREGS1Register (Address: 0Eh—Default Value: 88h)
TPS65014
SLVS551–DECEMBER 2004
Bit 6-Bit 4 - CORE<2:0>: The following table shows all possible values of VCORE. The default value can
subsequently be overwritten via the serial interface after start-up.
CORE2
0
0
0
0
1
1
1
1
CORE1
0
0
1
1
0
0
1
1
CORE0
0
1
0
1
0
1
0
1
VCORE
0.85 V
1.0 V
1.1 V
1.2 V
1.3 V
1.4 V
1.5 V
1.8 V
Bit 3-Bit 2 - CORELP<1:0>: CORELP1 and CORELP0 can be used to set the VCORE voltage in low power
mode. In low power mode, CORE2 is effectively
0
, and CORE1, CORE0 take on the values programmed at
CORELP1 and CORELP0, default
10
giving VCORE = 1.1 V as default in low power mode. When low power
mode is exited, VCORE reverts to the value set by CORE2, CORE1, and CORE0.
Bit 1 - VIB:
0 = disables the VIB output transistor.
1 = enables the VIB output transistor to drive the vibrator motor.
Bit 0 - CORE DISCHARGE:
0 = disables the active discharge of the VCORE converter output.
1 = enables the active discharge of the VCORE converter output in WAIT mode, or if VDCDC2 < 7 >= 1 in
LOW POWER mode.
VREGS1
Bit name
B7
B6
B5
B4
B3
B2
B1
B0
LDO2 enable
LDO2 OFF /
nSLP
0
R/W
LDO21
LDO20
LDO1 enable
LDO1 OFF /
nSLP
0
R/W
LDO11
LDO10
Default
Read/write
1
0
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
The VREGS1 register is used to program and enable LDO1 and LDO2 and to set their behavior when low power
mode is active. The LDO output voltages can be set either on the fly, while the relevant LDO is disabled, or
simultaneously when the relevant enable bit is set. Note that both LDOs are per default ON.
Bit 7-Bit 6 - The function of the LDO2 enable and LDO2 OFF/nSLP bits is shown in the following table. See the
power-on sequencing section for details of low power mode.
LDO2 ENABLE
0
1
1
LDO2 OFF / nSLP
X
0
1
LDO STATUS IN NORMAL MODE
OFF
ON, full power
ON, full power
LDO STATUS IN LOW-POWER MODE
OFF
ON, reduced power/performance
OFF
Bit 5-Bit 4 - LDO2<1:0>: LDO2 has a default output voltage of 1.8 V. If desired, this can be changed at the same
time as it is enabled via the serial interface.
LDO21
0
0
1
1
LDO20
0
1
0
1
VLDO2
1.8 V
2.5 V
3.0 V
3.3 V
47
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