參數(shù)資料
型號: TPS56300PWPR
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: 2 A DUAL SWITCHING CONTROLLER, 400 kHz SWITCHING FREQ-MAX, PDSO28
封裝: GREEN, PLASTIC, HTSSOP-28
文件頁數(shù): 5/39頁
文件大?。?/td> 1063K
代理商: TPS56300PWPR
TPS56300
DUALOUTPUT LOW INPUT VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261B DECEMBER 1999 SEPTEMBER 2000
13
www.ti.com
electrical characteristics TJ = 40° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)
VSENSERR and VSENSELDO discharge
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VSENSERR discharge FET current satura-
tion
VSENSERR = 1.5 V,
See Note 2
5
mA
VSENSERR discharge series resistance
(limits current)
INHIBIT = 0 V,
VIN = 5.5 V
1
k
VSENSERR discharge FET propagation
delay time
See Note 2
100
ns
VSENSELDO discharge FET current satu-
ration
VSENSELDO = 3.3 V,
See Note 2
5
mA
VSENSELDO discharge series
resistance (limits current)
INHIBIT = 0 V,
VIN = 5.5 V,
1
k
VSENSELDO discharge FET
propagation delay time
See Note 2
100
ns
NOTE 2. Ensured by design, not production tested.
detailed description
reference/voltage identification
The reference/voltage identification (VID) section consists of a temperature compensated bandgap reference and
a 2-pin voltage selection network. Both ripple regulator and LDO reference voltages are programmed with each VID
setting. The 2 VID pins are inputs to the VID selection network and are tri-level inputs that may be set to GND, floating
(internally 2.5V), or VDRV. The VID codes allow the controller to power both current and future DSP products. The
output voltages may also be programmed by external resistor voltage dividers for any values not included in the VID
code settings. Refer to Table 1 for the VID code settings. The output voltages of the VID network, VREFRR &
VREFLDO, are within 1.5% of the nominal setting for all the VID range of 1.3V to 3.3V. The reference tolerance
conditions include a junction temperature range of 40
°C to +125°C and a VCC supply voltage range of 2.8 V to 5.5
V. The VREFRR output of the reference/VID network is indirectly brought out through a buffer to the VREFB pin.
The voltage on this pin will be within 1.5% of VREFRR. It is not recommended to drive loads with VREFB, other than
setting the hysteresis of the hysteretic comparator, because the current drawn from VREFB sets the charging current
for the slowstart capacitor. Refer to the Slowstart section for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is set by
2 external resistors and is centered around VREF. The 2 external resistors form a resistor divider from VREFB to
ANAGND, and the divided down voltage connects to the VHYST pin. The hysteresis of the comparator will be equal
to twice the voltage difference that is across the VREFB and VHYST pins. The propagation delay from the comparator
inputs to the driver outputs is 250 ns maximum. The maximum hysteresis setting is 60 mv.
low-side driver
The low-side driver is designed to drive low Rds(on) logic-level N-channel MOSFETs. The current rating of the driver
is 2 amps typical, source and sink. The bias to the low-side driver is internally connected to the regulated synchronous
charge pump output.
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