參數(shù)資料
型號: TPS56300PWP
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: 2 A DUAL SWITCHING CONTROLLER, 400 kHz SWITCHING FREQ-MAX, PDSO28
封裝: GREEN, PLASTIC, HTSSOP-28
文件頁數(shù): 7/39頁
文件大?。?/td> 1063K
代理商: TPS56300PWP
TPS56300
DUALOUTPUT LOW INPUT VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261B DECEMBER 1999 SEPTEMBER 2000
15
www.ti.com
detailed description (continued)
slowstart
The slowstart circuit controls the rate at which VOUTRR and VOUTLDO power up (at same time). A capacitor is
connected between the SLOWST and ANAGND pins and is charged by an internal current source. The value of the
current source is proportional to the reference voltage, so that the charging rate of Cslowst is proportional to the ripple
regulator reference voltage. The slowstart charging current is determined by the following equation:
I
SLOWSTART +
I
VREFB
5
Where IVREFB is the current flowing out of the VREFB pin. It is recommended that no additional loads be connected
to VREFB, other than the resistor divider for setting the hysteresis voltage. Thus these resistor values will determine
the slowstart charging current. The maximum current that can be sourced by the VREFB circuit is 500
A. The
equation for the slowstart time is:
T
SLOWSTART +
5
C
SLOWSTART
R
VREFB
Where RVREFB is the total external resistance from VREFB to ANAGND.
power good
The power good circuit monitors for an undervoltage condition on VOUTRR and VOUTLDO. The powergood
(PWRGD) pin is pulled low if either VOUTRR is 7% below VREFRR, or VOUTLDO is 7% below VREFLDO.
PWRGD is an open drain output. The powergood pin is also pulled down, if either VCC or VDRV are below their UVLO
thresholds.
overvoltage protection
The overvoltage protection circuit monitors VOUTRR and VOUTLDO for an overvoltage condition. If VOUTRR
or VOUTLDO are 15% above their reference voltage, then a fault latch is set and both output drivers and LDO are
turned off. The latch will remain set until the VCC or inhibit voltages go below their undervoltage lockout values. A 1-s
to 5
s deglitch timer is included for noise immunity.
overcurrent protection
The overcurrent protection circuit monitors the current through the high-side FET. The overcurrent threshold is
adjustable with an external resistor divider between IOUT and ANAGND pins, with the divider voltage connected to
the OCP pin. If the voltage on the OCP pin exceeds 125 mV, then a fault latch is set and the output drivers are turned
off. The latch will remain set until the VCC or inhibit voltages go below their undervoltage lockout values. A 1-s to
5-
s deglitch timer is included for noise immunity. The OCP circuit is also designed to protect the high-side power
FET against a short-to-ground fault on the terminal common to both power FETs.
undervoltage protection
The undervoltage protection circuit monitors VOUTRR and VOUTLDO for an undervoltage condition. If VOUTRR
or VOUTLDO is 15% below their reference voltage, then a fault latch is set and both output drivers and LDO are
turned off. The latch will remain set until the VCC or inhibit voltages go below their undervoltage lockout values. A
100-
s to 1-ms deglitch timer is included for noise immunity.
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