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參數(shù)資料
| 型號： | TPS56300PWP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2 A DUAL SWITCHING CONTROLLER, 400 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | GREEN, PLASTIC, HTSSOP-28 |
| 文件頁數(shù)： | 6/39頁 |
| 文件大?。?/td> | 1063K |
| 代理商： | TPS56300PWP |
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TPS56300
DUALOUTPUT LOW INPUT VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS261B DECEMBER 1999 SEPTEMBER 2000
14
www.ti.com
detailed description (continued)
high-side driver
The high-side driver is designed to drive low Rds(on) logic-level N-channel MOSFETs. The current rating of the driver
is 2 amps typical, source and sink. The high-side driver can be configured either as a floating bootstrap driver or as
a ground-reference driver. When configured as a floating driver, the bias voltage to the driver is developed from the
charge pump VDRV voltage. The internal synchronous bootstrap rectifier, connected between the VDRV and BOOT
pins, is a synchronously-rectified MOSFET for improved drive efficiency. The maximum voltage that can be applied
between the BOOT pin and ground is 14 V. The driver can be referenced to ground by connecting BOOTLO to
DRVGND, and connecting a voltage
≥ (4.5 V + VCC) to the BOOT pin.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turn-on time of the MOSFET drivers. The high-side driver is not allowed to turn
on until the gate drive voltage to the low-side FET is below 1 V, and the low-side driver is not allowed to turn on until
the voltage at the junction of the 2 FETs (Vphase) is below 2 V.
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FET while the high-side
FET is on. The sampling network consists of an internal 60-
switch and an external hold capacitor. Internal logic
controls the turnon and turnoff of the sample/hold switch such that the switch does not turn on until the Vphase voltage
transitions high, and the switch turns off when the input to the high-side driver goes low. Thus sampling will occur only
when the high-side FET is conducting current. The voltage on the IOUT pin equals 2 times the sensed high-side
voltage.
droop compensation
The droop compensation network reduces the load transient overshoot / undershoot on VOUT, relative to VREF (see
application information for more details). VOUT is programmed to a voltage greater than VREF by an external resistor
divider from VOUT to the VSENSE pin to reduce the undershoot on VOUT during a low to high load transient. The
overshoot during a high to low load transient is reduced by subtracting the voltage that is on the DROOP pin from
VREF. The voltage on the IOUT pin is divided down with an external resistor divider, and connected to the DROOP
pin.
inhibit
INHIBIT is a TTL compatible comparator pin that is used to enable the controller. When INHIBIT is lower than the
threshold, the output drivers are low and the slowstart capacitor is discharged. When INHIBIT goes high (above 2.1
V), the short across the slowstart capacitor is released and normal converter operation begins. When another system
logic supply is connected to the INHIBIT pin, this pin controls power sequencing by locking out controller operation
until the system logic supply exceeds the input threshold voltage of the inhibit circuit; thus the +3.3-V supply and
another system logic supply (either +5 V or +12 V) must be above UVLO thresholds before the controller is allowed
to start up. Toggling the INHIBIT pin down clears the fault latch.
VCC & VDRV undervoltage lockout
The VCC undervoltage lockout circuit disables the controller while the VCC supply is below the 2.8-V start threshold.
The VDRV undervoltage lockout circuit disables the controller while the VDRV supply is below the 4.9 V start
threshold during powerup. While the controller is disabled, the output drivers will be low, the LDO drive is off, and the
slowstart capacitor will be shorted. When VCC and VDRV exceed the start threshold, the short across the slowstart
capacitor is released and normal converter operation begins.
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