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參數(shù)資料
| 型號： | TPS5625CPWPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, PDSO28 |
| 封裝： | PLASTIC, TSSOP-28 |
| 文件頁數(shù)： | 22/25頁 |
| 文件大?。?/td> | 387K |
| 代理商： | TPS5625CPWPR |
TPS5615, TPS5618, TPS5625, TPS5633
SYNCHRONOUS-BUCK HYSTERETIC REGULATOR CONTROLLER
SLVS177A – SEPTEMBER 1998 – REVISED NOVEMBER 1998
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
R2
+ 2.1
R1
V
TRIP
–2.1
Where
VTRIP=desired VSUPPLY trip voltage
R2
INHIBIT
TPS56xx
R1
To Power Stage
SHUTDOWN
VCC
Figure 4. Input Undervoltage Lockout Circuit Using INHIBIT
VCC undervoltage lockout (UVLO)
The undervoltage lockout circuit disables the controller while the VCC supply is below the 10-V start threshold
during power-up. While the controller is disabled, the output drivers will be low and the slowstart capacitor will
be shorted. When VCC exceeds the start threshold, the short across the slowstart capacitor is released and
normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise
immunity.
slowstart
The slowstart circuit controls the rate at which VO powers up. A capacitor is connected between SLOWSST and
ANAGND and is charged by an internal current source. The slowstart charging current is determined by the
following equation:
I
SLOWSTART +
I(VREFB)
5
where I(VREFB) is the current flowing out of VREFB. It is recommended that no additional loads be connected
to VREFB, other than the resistor divider for setting the hysteresis voltage. The maximum current that can be
sourced by the VREFB circuit is 500
A. The slowstart time is set by:
t
SLOWSTART +
5
C
SLOWST
R
VREFB
where RVREFB is the total external resistance from VREFB to ANAGND.
power good
The power good circuit monitors for an undervoltage condition on VO. If VO is 7% below VREF, then PWRGD
is pulled low. PWRGD is an open-drain output.
overvoltage protection
The overvoltage protection (OVP) circuit monitors VO for an overvoltage condition. If VO is 15% above VREF,
then a fault latch is set and both output drivers are turned off. The latch will remain set until VCC goes below the
undervoltage lockout value. A 3-
s deglitch timer is included for noise immunity. Refer to the LODRV section
for information on how to protect the load against overvoltages due to a shorted fault across the high-side power
FET.
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