參數(shù)資料
型號(hào)： TPS54880PWPR
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： 12 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
封裝： GREEN, PLASTIC, HTSSOP-28
文件頁(yè)數(shù)： 6/22頁(yè)
文件大?。?/td> 668K
代理商： TPS54880PWPR
TPS54880
SLVS450A OCTOBER 2002 REVISED APRIL 2005
www.ti.com
14
DETAILED DESCRIPTION
UNDERVOLTAGE LOCK OUT (UVLO)
The TPS54880 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 3.8 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
3.5 V. Hysteresis in the UVLO comparator, and a 2.5-s
rising and falling edge deglitch circuit reduce the likelihood
of shutting the device down due to noise on VIN.
TRACKIN/INTERNAL SLOW-START
The internal slow-start circuit provides start-up slope
control of the output voltage. The nominal internal
slow-start rate is 25 V/ms. When the voltage on TRACKIN
rises faster than the internal slope or is present when
device operation is enabled, the output rises at the internal
rate. If the reference voltage on TRACKIN rises more
slowly, then the output rises at about the same rate as
TRACKIN.
Once the voltage on the TRACKIN pin is greater than the
internal reference of 0.891 V, the multiplexer switches the
noninverting node to the high precision reference.
ENABLE (ENA)
The enable pin, ENA, provides a digital control enable or
disable (shut down) for the TPS54880. An input voltage of
1.4 V or greater ensures that the TPS54880 is enabled. An
input of 0.82 V or less ensures that device operation is
disabled. These are not standard logic thresholds, even
though they are compatible with TTL outputs.
When ENA is low, the oscillator, slow-start, PWM control
and MOSFET drivers are disabled and held in an initial
state ready for device start-up. On an ENA transition from
low to high, device start-up begins with the output starting
from 0 V.
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor must be placed close
to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that
internal circuits require a minimum VBIAS of 2.70 V, and
external loads on VBIAS with ac or digital switching noise
may degrade performance. The VBIAS pin may be useful
as a reference voltage for external circuits.
VOLTAGE REFERENCE
The voltage reference system produces a precise Vref
signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and
scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected
as a voltage follower. The trim procedure adds to the high
precision regulation of the TPS54880, since it cancels
offset errors in the scale and error amplifier circuits.
OSCILLATOR AND PWM RAMP
The oscillator frequency is set internally to 350 kHz. If a
different frequency of operation is required for the
application, the oscillator frequency can be externally
adjusted from 280 to 700 kHz by connecting a resistor
between the RT pin and AGND. The switching frequency
is approximated by the following equation, where R is the
resistance from RT to AGND:
Switching Frequency + 100 kW
R
500 [kHz]
SWITCHING FREQUENCY
RT PIN
350 kHz, internally set
Float
Externally set 280 kHz to 700 kHz
R = 180 k to 68 k
ERROR AMPLIFIER
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54880 apart from most dc/dc
converters. The user is given the flexibility to use a wide
range of output L and C filter components to suit the
particular application needs. Type 2 or type 3 compensa-
tion can be employed using external compensation
components.
PWM CONTROL
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is reset, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset, and the high-side FET remains on until
(2)
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