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參數(shù)資料
| 型號： | TPS54880EVM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-Amp SWIFT Regulator Evaulation Module(8A SWIFT穩(wěn)壓器TPS54880的評估模塊) |
| 中文描述： | 8安培的SWIFT穩(wěn)壓Evaulation模塊（8A條SWIFT的穩(wěn)壓器TPS54880的評估模塊） |
| 文件頁數(shù)： | 16/44頁 |
| 文件大小： | 1180K |
| 代理商： | TPS54880EVM |
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Tracking Regulator and Power Sequencing
1-6
1.3
Tracking Regulator and Power Sequencing
To avoid potential problems with the processor and system ICs, designers can
apply three general techniques for power-up sequencing: sequential,
ratiometric, or simultaneous. Sequential power up, as the name implies,
powers up the two rails one after the other. Typically the second rail begins to
ramp up once the first rail reaches regulation. Alternately, the second rail may
begin its ramp after a set delay from the start of the first rail. Either method must
comply with the processor manufacturer
’
s restriction on the minimum and
maximum time one supply is not powered, or the duration and amount that one
supply exceeds the other. With the second or ratiometric method, the two rails
begin to power up and reach regulation at the same time. This requires a
higher slew rate for the rail with the higher final voltage, and results in the
maximum voltage differential occurring when regulation is reached. However,
some processors may not tolerate the instantaneous voltage differences that
occur before regulation is reached, or the processor may draw high current
from one supply during this period. The third approach eliminates
instantaneous voltage differences and minimizes the magnitude and duration
of stresses. A common way of implementing this method is simultaneous
power up, in which the voltage rails rise together and at the same rate, with the
higher or I/O voltage rail continuing after the lower or core voltage rail has
reached its final value.
The TPS54x80EVM-228 evaluation module is designed to demonstrate the
described power sequencing technique. The basic idea is shown in
Figure 1-1.
Figure 1-1.
Different Power Sequencing Technique Selection
I/O Regulator
VSENSE
R1
R2
TPS54x80
Core Tracking
Regulator
VSENSE
R5
R6
TRACKIN
R3
R4
V I/O
V
(core)
Implementation of different power sequencing techniques is based on proper
resistor-divider ratio selection. The equations 1, 2, and 3 provide related ratios
for different ways of power sequencing.
R3
R4
R3
R4
R3
R4
R5
R6
R1
R2
R5
R6
–
core voltage tracks I O voltage (simultaneous power up)
–
ratiometric relation between core and I O voltage
core voltage rises first at power up and falls second at power down.
(1)
(2)
(3)
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